Integrated memory circuit with interconnected sense amplifiers

Details Integrated memory circuit with interconnected sense amplifiers Integrated memory circuit with interconnected sense amplifiers

1989-11-30

1992-01-21

Bowler, Alyssa H.

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

36518904, 365207, 365208, 307530, G11C 700, G11C 11409

Patent

active

050832956

ABSTRACT:
An integrated circuit with a memory, includes a matrix of memory cells and sense amplifiers which are coupled thereto, with the inputs of the sense amplifiers being connected to one another and the outputs of the sense amplifiers being connected to one another via a read bus. During the reading of information from a memory cell, the sense amplifiers are simultaneously activated. As a result, the access time for reading information from a a memory cell remains substantially constant when the number of memory columns to be connected in parallel is changed. The dimensioning of the sense amplifiers may remain the same when the number of memory columns is changed, so that dimensioning need be performed only once. This results in a saving as regards time and costs.

REFERENCES:
patent: 3879621 (1975-04-01), Cavaliere et al.
patent: 4131951 (1978-12-01), Asahi
patent: 4555777 (1985-11-01), Poteet
patent: 4804871 (1989-02-01), Walters, Jr.
patent: 4813021 (1989-03-01), Kai et al.
patent: 4879692 (1989-11-01), Tokushige
IBM-TDB vol. 28, No. 3, Aug. 1985: "Bitline Restore Circuit for High Speed CMOS Arrays" pp. 1227-1228.
IBM-TDB vol. 18, No. 6, Nov. 1975: "Read and Write For Random Access Memory Array" pp. 1849-1850.
IBM-TDB vol. 29, No. 5, Oct. 1986 "Dense Sense Amplifier/Latch Combination" pp. 2160-2161.

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