Integrated memory circuit having a differential read amplifier

Details Integrated memory circuit having a differential read amplifier Integrated memory circuit having a differential read amplifier

1987-12-22

1989-05-16

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Flip-flop

365174, 365207, 36518911, G11C 700, G11C 1140

Patent

active

048315885

ABSTRACT:
A monolithic integrated memory includes a differential read amplifier circuit which is associated with a column of the memory and which has two source-coupled field effect transistors, the coupling point of which is controlled by a current source which itself is controlled by the output signal of a decoder stage which enables the selection of the memory column. The gate of each coupled transistor receives the signal of a bit line of the memory column, while the drains of the coupled transistors apply a signal to the read bus of the memory. A translator circuit is provided for translating the levels of the signals transported by the bit lines in order to ensure that these levels are at most equal to the levels of the signals transported by the read bus, so that the gate-drain capacitances of the coupled transistors of the differential amplifier are negligibly small.

REFERENCES:
patent: 4208730 (1980-06-01), Dingwall et al.
patent: 4507759 (1985-03-01), Yasui et al.

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