Integrated memory circuit and method for repairing a single...

Static information storage and retrieval – Read/write circuit – Bad bit

Reexamination Certificate

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C365S201000

Reexamination Certificate

active

07372750

ABSTRACT:
The invention relates to an integrated memory circuit having a memory cell array comprising memory cells arranged on word lines and bit lines, and having a repair circuit for repairing a single bit error in one of the memory cells, the repair circuit comprising: an error memory for storing an item of repair information, an assignment unit in order, when accessing an address of the memory cell array, depending on the repair information, to access either a memory area of the memory cell array or a redundancy memory area, and a test unit for determining the repair information. The test unit comprises a write unit, which successively writes first test data and second test data to a plurality of memory cells of a memory area of the memory cell array, a read-out unit which reads out data stored in the memory area, a modification unit in order to modify the bits of the read-out data in such a way that the position of each bit changes and each of the bits is inverted in order to provide the second test data, which are subsequently written to the memory area with the aid of the write unit, and a comparator unit in order to compare the data read out after the writing of the second test data with expected data and to provide the repair information depending on the comparison result.

REFERENCES:
patent: 5598373 (1997-01-01), Wada et al.
patent: 6650583 (2003-11-01), Haraguchi et al.
patent: 7085182 (2006-08-01), Collura et al.
patent: 7155643 (2006-12-01), Ichikawa
patent: 197 25 581 (1999-01-01), None
patent: 102 14 209 (2003-10-01), None

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