Integrated memory cell and method of fabrication

Details Integrated memory cell and method of fabrication Integrated memory cell and method of fabrication

1999-12-03

2003-02-11

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S333000, C257S336000, C257S344000, C257S371000, C257S387000, C257S389000, C257S412000

Reexamination Certificate

active

06518618

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor manufacturing and more specifically to a nonvolatile memory cell and its method of fabrication.
2. Discussion of Related Art
A conventional electrically erasable nonvolatile memory cell
100
is shown in FIG.
1
. Memory cell
100
includes an n+ polysilicon floating gate
102
formed on the tunnel oxide
104
which is formed on the p-type silicon region
106
. An interpoly dielectric
108
is formed on the n+ polysilicon floating gate and a control gate
110
formed on the interpoly dielectric layer
108
and a pair of n+ source/drain regions
109
are formed along laterally opposite sidewalls of floating gate electrode
102
. Memory cell
100
includes fully landed metal contacts
120
which are formed entirely on the source/drain regions. To store information in memory device
100
charge is stored on floating gate
102
. To erase memory device
100
charge is removed from floating gate
102
.
A problem with memory storage cell
100
shown in
FIG. 1
, is that it has become difficult to further scale down its width and length to form smaller area cells and higher density memory circuits. For example, using contacts which are fully landed on diffusion requires a wider diffusion spacing than required for the memory cell transistor. Fully landed contacts require a large contact to gate and isolation spacing. Fully landed contacts prevent the reduction of both cell width and length. Additionally, floating gate
102
is formed by standard lithographic techniques with the cell width being limited by the minimum space resolution and the minimum registration. Another problem with cell
100
is that is suffers from charge leakage whereby electrons leak off the floating gate. In order to prevent charge leakage, the source junction is typically heavily graded leading to large under diffusion and a long gate length. Charge leakage also requires product level device optimization of voltages for balancing adequate read current verses charge loss margins thereby creating complexities in circuit design. Additionally, prevention of charge leakage also requires relatively thick tunnel oxides which in turn prevents the scaling of the device gate length.
SUMMARY OF THE INVENTION
A nonvolatile memory cell comprising a pair of spaced apart shallow trench isolation regions formed in a substrate and defining a substrate active region. A tunnel dielectric is formed on the substrate active region. A floating gate is formed on the tunnel dielectric and is self aligned between the spaced apart shallow trench isolation regions. A dielectric layer is formed on the floating gate and a control gate formed on the dielectric layer. A source region and a drain region are formed in the substrate active region on opposite sides of the floating gate.


REFERENCES:
patent: 3660819 (1972-05-01), Frohman-Bentchkowsky
patent: 3728695 (1973-04-01), Frohman-Bentchkowsky
patent: 3744036 (1973-07-01), Frohman-Bentchkowsky
patent: 3755721 (1973-08-01), Frohman-Bentchkowsky
patent: 4203158 (1980-05-01), Frohman-Bentchkowsky
patent: 5260593 (1993-11-01), Lee
patent: 5293512 (1994-03-01), Nishigoori et al.
patent: 5511020 (1996-04-01), Hu et al.
patent: 5616942 (1997-04-01), Song
patent: 5650649 (1997-07-01), Tsukiji
patent: 5766997 (1998-06-01), Takeuchi
patent: 5864157 (1999-01-01), Fu
patent: 5901084 (1999-05-01), Ohnakado
patent: 6008112 (1999-12-01), Acocella et al.
patent: 6060360 (2000-05-01), Lin et al.
patent: 6060741 (2000-05-01), Huang
patent: 6097070 (2000-08-01), Mandelman et al.
patent: 6201275 (2001-03-01), Kawasaki et al.
patent: 4114166 (1992-02-01), None
patent: 0 085 551 (1983-08-01), None
patent: 0085551 (1983-10-01), None
patent: 0649172 (1995-04-01), None
patent: 1383981 (1975-02-01), None
patent: 03198377 (1991-08-01), None
patent: 09129757 (1997-05-01), None
patent: 09260517 (1997-10-01), None
patent: 10135357 (1998-05-01), None
IBM Tech. Dis. Bul., vol. 36, No. 02, Feb 1993, “Planarized NVRAM Cell with Self-aligned BL-BL and WL-BL Isolations”.*
International Search Report, PCT/US00/22784, Aug. 17, 2000.
International Written Opinion, PCT/US00/22784, Aug. 17, 2000.
C. Salm et al. “Gate Current and Oxide Reliability in p+ Poly MOS Capacitors with Poly-Si and Poly-Ge0.3 Si0.7 Gate Material”, IEEE Electron Device Letters, vol. 19, No. 7, Jul. 1998, pp. 213-215.
V.E. Houtsma et al., DC-SILC in p+ Poly MOS Capacitors with Poly-Si0.7 and Ge0.3 Gate Material, 29thIEEE Semiconductor Interface Specialist Conference, San Diego, CA Dec. 3-5, 1998.
Steven C. Chung et al., “A Novel High Performance and Reliability p-Type Floating Gate N-Channel Flash EEPROM”, 1999 Symposium on VLSI Technology Digest of Technical Papers.
Ying Shi et al., “Polarity Dependent Gate Tunneling Currents in Dual-Gate CMOSFETs” Abstracts, Center for Microelectronic Materials & Structures and Dept of Electrical Engineering, Yale University, New Haven, CT, IEEE Member.
Ying Shi et al., “Polarity-Dependent Tunneling Currents and Oxide Breakdown in Dual-Gate CMOSEFTs”, IEEE Transactions on Electron Devices, vol. 45, No. 11, Nov. 1998, pp. 391-393.
Ying Shi et al., “Polarity Dependent Gate Tunneling Currents in Dual-Gate CMOSFETs” IEEE Transactions on Electron Devices, vol. 45, No. 11, Nov. 1998, pp. 2355-2360.
Murray H. Woods, “An E-PROM's Integrity Starts With its Cell Structure” Intel Corporation, Santa Clara, CA, Aug. 14, 1980.

Affiliated with

Also associated with

Rating

Integrated memory cell and method of fabrication does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated memory cell and method of fabrication, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated memory cell and method of fabrication will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3146187