Integrated memory cell and method of fabrication

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S333000, C257S336000, C257S344000, C257S371000, C257S387000, C257S389000, C257S412000

Reexamination Certificate

active

06518618

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor manufacturing and more specifically to a nonvolatile memory cell and its method of fabrication.
2. Discussion of Related Art
A conventional electrically erasable nonvolatile memory cell
100
is shown in FIG.
1
. Memory cell
100
includes an n+ polysilicon floating gate
102
formed on the tunnel oxide
104
which is formed on the p-type silicon region
106
. An interpoly dielectric
108
is formed on the n+ polysilicon floating gate and a control gate
110
formed on the interpoly dielectric layer
108
and a pair of n+ source/drain regions
109
are formed along laterally opposite sidewalls of floating gate electrode
102
. Memory cell
100
includes fully landed metal contacts
120
which are formed entirely on the source/drain regions. To store information in memory device
100
charge is stored on floating gate
102
. To erase memory device
100
charge is removed from floating gate
102
.
A problem with memory storage cell
100
shown in
FIG. 1
, is that it has become difficult to further scale down its width and length to form smaller area cells and higher density memory circuits. For example, using contacts which are fully landed on diffusion requires a wider diffusion spacing than required for the memory cell transistor. Fully landed contacts require a large contact to gate and isolation spacing. Fully landed contacts prevent the reduction of both cell width and length. Additionally, floating gate
102
is formed by standard lithographic techniques with the cell width being limited by the minimum space resolution and the minimum registration. Another problem with cell
100
is that is suffers from charge leakage whereby electrons leak off the floating gate. In order to prevent charge leakage, the source junction is typically heavily graded leading to large under diffusion and a long gate length. Charge leakage also requires product level device optimization of voltages for balancing adequate read current verses charge loss margins thereby creating complexities in circuit design. Additionally, prevention of charge leakage also requires relatively thick tunnel oxides which in turn prevents the scaling of the device gate length.
SUMMARY OF THE INVENTION
A nonvolatile memory cell comprising a pair of spaced apart shallow trench isolation regions formed in a substrate and defining a substrate active region. A tunnel dielectric is formed on the substrate active region. A floating gate is formed on the tunnel dielectric and is self aligned between the spaced apart shallow trench isolation regions. A dielectric layer is formed on the floating gate and a control gate formed on the dielectric layer. A source region and a drain region are formed in the substrate active region on opposite sides of the floating gate.


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