Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2002-03-05
2003-07-08
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000
Reexamination Certificate
active
06590816
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention lies in the integrated technology field. More specifically, the invention relates to an integrated memory having memory cells arranged in a memory cell block having a plurality of column lines and a plurality of row lines. The invention furthermore relates to a method for testing and repairing an integrated memory of that type.
Manufacturers generally test integrated semiconductor memories for functionality and repair them as far as possible before delivery of the memories. To that end, the semiconductor memories have not only regular memory cells but also redundant memory cells which can replace a certain proportion of the regular memory cells in the case of defects that have been ascertained. In this context, the redundant memory cells are generally combined in the same way as the regular memory cells to form row lines (word line, WL) and column lines (bit line, BL).
A redundancy concept of this type makes it possible to increase the chip yield during production. After chip fabrication, memory defects are determined by targeted testing and recorded in a defect log. Programmable elements, for example a series of so-called laser fuses, are then used to exchange, in address terms, individual defective row lines or column lines for defect-free redundant row or column lines, respectively.
If laser fuses are used as the programmable elements, then defective row or column lines can only be replaced during the tests at the wafer level. The laser fuses are no longer accessible to the programming laser beam once the chip has been incorporated into a housing.
If electrically programmable fuses, so-called e-fuses, are used as programmable elements, redundancy activation is possible even after the chips have been incorporated into a housing. This is utilized primarily when module defects are not discovered until late in the production or test sequence.
After delivery of the modules, defect correction through the exchange of redundant elements no longer takes place. Defects that occur at this stage lead at worst to the failure of the module and to a return to the manufacturer. In order to preclude this risk, the devices are usually subjected to so-called stress tests, the aim of which is to get as far as possible all susceptible devices to fail whilst still in the test phase with the manufacturer, so that the purchaser only acquires already repaired modules with a low failure probability for the future. However, such stress tests are time-consuming and costly. Moreover, they cannot reduce the failure rate of regular modules after delivery.
This forms the starting point for the invention.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a integrated memory device and a method of testing and repairing the same, which overcome the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which provides for an integrated memory with a low failure probability after delivery.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory, comprising:
a plurality of memory cells arranged in a memory cell block having a plurality of column lines and a plurality of row lines;
the plurality of row lines including regular row lines and redundant row lines;
a self-test unit connected to the memory cell block, the self-test unit:
upon a read access to a current row line, checking for a correctness of a memory cell content read in the read access and, upon detecting a defect, generating a defect signal for the current row line;
for each regular row line, detecting defects thus ascertained and performing a comparison comparing the defects with an average defect for all the regular row lines; and
outputting a row repair signal for the current row line when a predetermined repair condition is met in the comparison;
a self-repair unit connected to the self-test unit, the self-repair unit, in response to receiving the row repair signal, replacing the current row line by a redundant row line during an operation of the integrated memory.
In accordance with an added feature of the invention, the plurality of column lines includes regular column lines and redundant column lines;
the self-test unit:
upon a read access to a current row line, checks the correctness of the memory cell contents read and, in an event of a defect, generates a defect signal for the current row line;
in case of an ascertained defect, compares a calculated signature of the memory cell contents with a previously stored signature, for determining the column line in which the defect occurred;
for each regular row line and for each regular column line, detects the defects ascertained and in each case performs a comparison comparing the defects with an average defect for all of the regular row lines and all of the regular column lines; and
when a predetermined repair condition is met during the comparison, outputs a row repair signal for the current row line or a column repair signal for a column line that has been identified as defective; and
the self-repair unit:
in response to a row repair signal, replaces the current row line by a redundant row line during the operation of the integrated memory; and
in response to a column repair signal, replaces the column line that has been identified as defective by a redundant column line.
In an alternative embodiment of the invention, there is provided an integrated memory, comprising:
memory cells arranged in a memory cell block having a plurality of column lines and a plurality of row lines;
the plurality of row lines including regular row lines and redundant row lines, and the plurality of column lines including regular column lines and redundant column lines;
a self-test unit connected to the memory cell block and configured to:
in an event of a read access to a current row line, check a correctness of the memory cell contents read and, upon detecting a defect, generate a defect signal for the current row line;
in case of an ascertained defect, compare a calculated signature of the memory cell contents with a previously stored signature, for determining a respective column line in which the defect occurred;
store the complete addresses of the memory cells in which a defect occurred successively in a shift register;
if an address of a same memory cell is repeatedly stored in the shift register, determine the row line and column line associated with the memory cell; and
when a predetermined repair condition is met, output a row repair signal for the associated row line or a column repair signal for the associated column line;
a self-repair unit connected to the self-test unit and configured to:
in response to a row repair signal, replace the current row line by a redundant row line during an operation of the integrated memory; and
in response to a column repair signal, replace the column line that has been identified as defective by a redundant column line.
With the above and other objects in view there is also provided, in accordance with the invention, a method of testing and repairing an integrated memory having memory cells arranged in a memory cell block with a plurality of column lines and a plurality of row lines, and wherein the plurality of row lines includes regular row lines and redundant row lines, the method which comprises the following steps:
reading memory cell contents of a current row line;
checking a correctness of the memory cell contents read;
generating a defect signal for the current row line in a defect case;
detecting the defects ascertained for each regular row line;
comparing a number of defects of the current row line with an average defect for all the regular row lines;
outputting a row repair signal for the current row line when a predetermined repair condition is met in the comparing step; and
replacing the current row line by a redundant row line in response to a row repair signal during an operation of the integrated memory.
In a further alternative of the invention—applicable w
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Phan Trong
Stemer Werner H.
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