Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2002-04-18
2003-10-28
Nguyen, Van Thu (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S207000, C365S208000
Reexamination Certificate
active
06639861
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to an integrated memory having a memory cell array, which has word lines for the selection of memory cells and bit lines for reading out or writing data signals from/to the memory cells. The bit lines, for reading out a data signal, can in each case be connected to a sense amplifier via a controllable switching device. The invention also relates to a method for testing an integrated memory of this type.
An integrated memory such as, for example, a memory of the DRAM type generally has one or more memory cell arrays each containing bit lines and word lines. The memory cells are disposed at crossover points between the bit lines and word lines. For the selection of the memory cells, selection transistors of respective memory cells are turned on by an activated word line, as a result of which a data signal of a selected memory cell can subsequently be read out or written. To that end, the selected memory cell is connected via the selection transistor to one of the bit lines, via which the respective data signal is read out or written in. The information read out from a memory cell in the event of a memory cell access is evaluated and amplified by a sense amplifier.
A memory cell array of an integrated memory is often subdivided into a plurality of segments which each adjoin one another. In this case, the bit lines run through each of the segments. Consequently, in the case of two memory segments, a bit line half of the respective bit line is disposed in each of the segments. In particular in the interests of a space-saving configuration, there is usually disposed between two segments in each case a sense amplifier which is assigned jointly to both segments and can be connected to the bit line halves of the respective bit line via a respective switching device.
In a deactivation state or precharge state, generally both bit line halves of the respective bit line are connected to the sense amplifier. For a memory cell access, the cell information of the selected memory cell passes first onto the bit line half connected to the memory cell and thus to the sense amplifier. The respective other bit line half of the selected bit line is disconnected from the sense amplifier via the corresponding switching device. This ensures that only one of the bit line halves is connected to the sense amplifier. Consequently, in each state of the bit line, at least one bit line half is connected to the sense amplifier. In this case, within an access cycle for reading out a data signal via a selected bit line, it is generally not possible, however, for both bit line halves connected to the sense amplifier to be simultaneously disconnected from the sense amplifier. Therefore, it is not possible to measure, for example, the leakage behavior of a bit line half to be read.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated memory and a method for testing an integrated memory which overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, in which it is possible to measure the leakage behavior of a bit line.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory. The memory contains a sense amplifier, a terminal for a test mode signal, and controllable switching devices connected to the sense amplifier and having control inputs. A memory cell array is provided and has memory cells, word lines connected to and selecting the memory cells, and bit lines connected to the memory cells for reading out or writing data signals to/from the memory cells. The bit lines are connected to the controllable switching devices and, for reading out a data signal, the bit lines in each case are coupled to the sense amplifier through one of the controllable switching devices. A control circuit having an output is connected to the control inputs of the controllable switching devices. The control circuit has an input connected to the terminal for the test mode signal. The control circuit is configured in such a way that, within an access cycle, a respective switching device of the controllable switching devices can be switched into a non-conducting state on account of an active state of the test mode signal.
The object relating to the integrated memory is achieved by an integrated memory of the type mentioned in the introduction having a control circuit with an output. The output is connected to a control input of the respective switching device. The control circuit has an input, which is connected to a terminal for a test mode signal in which the control circuit is configured in such a way that, within an access cycle, the respective switching device an be switched into a non-conducting state on account of an active state of the test mode signal.
The present integrated memory according to the invention makes it possible to measure the leakage behavior of a bit line when a data signal is read out via the relevant bit line, to be precise without the influence of the sense amplifier. For this purpose, use is made of a corresponding control circuit that, on account of an active state of the test mode signal, puts the respective switching device into the non-conducting state within an access cycle. As a result, the relevant bit line is no longer connected to the sense amplifier and the leakage behavior of the bit line can be measured without the influence of the sense amplifier.
In one embodiment of the method according to the invention, the bit lines are in each case disposed in at least two mutually adjoining segments of the memory cell array, so that a bit line half of the respective bit line is disposed in each of the segments. The sense amplifier is disposed between the two segments and can be connected to the bit line halves of the respective bit line via a respective switching device.
In a further embodiment, in a deactivation state, the bit line halves of the respective bit line are connected to the sense amplifier. In the event of a memory cell access, one of the bit line halves of the selected bit line is connected to the sense amplifier, and the respective other of the bit line halves of the selected bit line is disconnected from the sense amplifier. That one of the bit line halves which is connected to the sense amplifier can be disconnected from the sense amplifier on account of the active state of the test mode signal.
This affords the advantage, in particular, that one bit line half can be disconnected independently of the other bit line half of the same bit line. Since the relevant bit line half via which the data signal is read out is no longer driven, the read-out signals can develop independently of the sense amplifier. If a leakage mechanism is present, then there is a change in the relevant potential state on the corresponding bit line half. This change in the potential state can subsequently be measured.
In accordance with an added feature the invention, a decoder circuit is provided and receives address signals for selecting one of the memory cells. The control circuit has a further input connected to the decoder circuit.
In accordance with a further feature of the invention, the decoder circuit is a word line decoder to which a word line address for selecting one of the word lines can be applied.
The object relating to the method is achieved by a method for testing an integrated memory according to the invention in which one of the memory cells is selected for reading out a stored data signal by the activation of one of the word lines. The data signal to be read out on a selected bit line is evaluated and amplified by the sense amplifier, in which afterward the test mode signal is activated for the purpose of disconnecting the selected bit line from the sense amplifier. A potential state of the selected bit line is written back to the memory cell after the disconnection, and in which the memory cell is selected again after the writing-back process. The potential state written back
Beer Peter
Benzinger Herbert
Schroeder Stephan
Stief Reidar
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Nguyen Van Thu
Stemer Werner H.
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