Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2006-12-26
2006-12-26
Nguyen, Tan T. (Department: 2827)
Static information storage and retrieval
Read/write circuit
Testing
C365S069000, C365S230030
Reexamination Certificate
active
07154793
ABSTRACT:
An integrated memory includes memory cells arranged in a memory cell array along word lines and bit lines. One of the bit lines can be connected to a data line by a respective one of a plurality of switches. The memory contains column select lines. One of the column select lines in each case connected to a plurality of the switches for driving, in an activated state, in order to connect a number of bit lines to a same number of data lines. An access controller is connected to the column select lines and can be operated in a test operating mode such that a plurality of the column select lines are activated in the event of a memory cell access. The writing of test data to the memory cell array in a test operating mode can thus be optimized in accordance with the invention.
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Funfrock Fabien
Sommer Michael Bernhard
Edell Shapiro & Finnan LLC
Infineon - Technologies AG
Nguyen Tan T.
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