Integrated memory and method for functional testing of the...

Static information storage and retrieval – Read/write circuit – Testing

Reexamination Certificate

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C365S069000, C365S230030

Reexamination Certificate

active

07154793

ABSTRACT:
An integrated memory includes memory cells arranged in a memory cell array along word lines and bit lines. One of the bit lines can be connected to a data line by a respective one of a plurality of switches. The memory contains column select lines. One of the column select lines in each case connected to a plurality of the switches for driving, in an activated state, in order to connect a number of bit lines to a same number of data lines. An access controller is connected to the column select lines and can be operated in a test operating mode such that a plurality of the column select lines are activated in the event of a memory cell access. The writing of test data to the memory cell array in a test operating mode can thus be optimized in accordance with the invention.

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patent: 5305265 (1994-04-01), Sugibayashi
patent: 5367492 (1994-11-01), Kawamoto et al.
patent: 5461589 (1995-10-01), Hidaka et al.
patent: 5726939 (1998-03-01), Cho et al.
patent: 6041002 (2000-03-01), Maejima
patent: 6574128 (2003-06-01), Morgan

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