Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2001-09-20
2003-04-01
Tran, M. (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S230010
Reexamination Certificate
active
06542430
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the integrated technology field. More specifically, the present invention relates to an integrated memory and a memory configuration having at least a first memory and a second memory and also to a method for operating a memory configuration having at least a first memory and a second memory.
Configurations such as, for example, personal computer systems (PC systems) generally have data processing devices in the form of microprocessors or micro-controllers and functional units such as program memories, data memories or input/output peripheral assemblies. The microprocessor thereby usually constitutes the central control and computation unit and is therefore also referred to as the so-called central processing unit (CPU). The data memory, which is generally embodied as a so-called random access memory (RAM), contains, for example, data which are accessed during a memory access. The electrical connection between the microprocessor and the data memory, for example, is usually established via a bus system.
It can generally be observed that, in order to increase the data throughput, microprocessors are operated with increasing processing speeds and hence increasing transmission frequencies as well. For this reason, in particular, it is endeavored likewise to increase the processing speed and transmission frequency on the corresponding bus systems, in order not to limit the overall performance of the PC system. However, this can generally lead to physical and/or electrical problems. Particularly in the case of comparatively long bus systems connected to a memory configuration having a plurality of memories or memory modules connected in parallel, increasing transmission frequencies can be accompanied by a high degree of reflection and interference of signals to be transmitted. This can impair the signal quality and hence the detect ability of the data to be transferred. This reflection and interference is caused for example by a multiplicity of memory modules connected in parallel and the—as a result—limited possibilities for suitable matching of the electrical parameters and/or by limited electrical properties of the bus systems and of the connected memory modules.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated memory and a memory configuration having at least a first memory and second memory, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which enables a comparatively high data throughput in each case with good detectability of the data to be transferred being maintained. It is a further object of the present invention to specify a method for operating a memory configuration having at least a first memory and a second memory, by means of which a comparatively high data throughput of the memory configuration, for example to a micro-controller, can be achieved with good detectability of the data to be transferred.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory, comprising:
a memory cell array for storing data;
first and second communications interfaces for data transfer each connected to a respective data bus system, and each operable independently of one another;
wherein the memory cell array can be connected to the data bus system for a memory cell access;
a comparison circuit connectible to the first communications interface, the comparison circuit comparing an address of data stored in the memory cell array with an address applied to the first communications interface, and activating the memory cell array for a memory cell access in dependence on a comparison result; and
a control circuit connectible to the comparison circuit and the second communications interface, for forwarding the applied address to the second communications interface in dependence on the comparison result of the comparison circuit.
There is also provided, in accordance with the invention, a memory configuration which comprises two or more memories as outlined above. The first communications interface of a first memory is connected to a communication bus and the second communications interface of the first memory is connected to the first communications interface of the second memory.
With the above and other objects in view there is also provided, in accordance with the invention, a method of operating a memory configuration having at least a first memory for storing data, first and second communications interfaces for data transfer to and from the first memory, and having a second memory for storing data, first and second communications interfaces for data transfer to and from the second memory, wherein the first communications interface of the second memory is connected to the second communications interface of the first memory, the method which comprises:
operating the first and second communications interfaces of the first and second memories independently of one another;
applying an address of requested data from outside the memory configuration to the first communications interface of the first memory;
ascertaining whether the applied address corresponds to an address of data stored in the first memory;
if the applied address corresponds to an address of data stored in the first memory, outputting stored data via the first communications interface of the first memory; and
if the applied address does not correspond to an address of data stored in the first memory, transferring the address of the requested data to the second communications interface of the first memory, receiving the requested data from the first communications interface of the second memory via the second communications interface of the first memory, and outputting the requested data via the first communications interface of the first memory.
The memory according to the invention and the memory configuration according to the invention make it possible to achieve a comparatively high data throughput of data to be transferred. This is achieved in particular by virtue of the fact that the communication bus connected to the first memory and the connection between the first memory and the second memory are electrically decoupled. This makes it possible to operate the communication bus and the bus system between the first memory and the second memory with comparatively high data transmission frequencies.
Moreover, the electrical isolation of the bus systems makes it possible to embody the bus systems in such a way that a no relatively low degree of signal reflection occurs. As a result, the signal quality and hence the transmission frequency, too, can be significantly increased. The memory configuration according to the invention creates so-called point-to-point connections of the bus systems which can be configured in such a way that a relatively low degree of reflection occurs even at relatively high signal frequencies. This makes it possible to increase the signal quality and thus the signal frequency. In addition, the creation of isolated bus systems means that it is not absolutely necessary to raise the electrical requirements made of the bus system connecting the two memories and also the electrical requirements made of the second memory itself or of the interface unit thereof.
The invention makes it possible, in particular, to realize memory systems that, in principle, are as large as desired, without having to reduce the data transmission frequency. The memory configuration according to the invention can, in principle, be expanded by as many memories or memory modules as desired. This constitutes a major advantage primarily for future server realizations, for example for the Internet.
The invention can advantageously be used in a main memory system of a PC system. The latter usually comprises a relatively long memory bus system to which one or more memory modules are connected, the memory modules generally being embodied as so-called RAMs.
The memory according to the inven
Mayback Gregory L.
Tran M.
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