Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2002-05-20
2004-04-27
Tran, M. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S193000
Reexamination Certificate
active
06728143
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present invention relates to an integrated memory having a memory cell array with memory cells and a control circuit for controlling a memory access for reading a data signal out from one of the memory cells or for writing a data signal to one of the memory cells.
An integrated memory generally has a memory cell array including word lines and bit lines. In this case, the memory cells are arranged at crossover points between the bit lines and the word lines. The memory cells are connected, via a respective selection transistor, to one of the bit lines so that a data signal can be read out and written in. The control input of the selection transistor is connected to one of the word lines. For a memory access, a control circuit for controlling the memory access generally receives an access command in the form of an activation command, a read command, or a write command. In order to read out or write a data signal, the respective selection transistor of the corresponding memory cell is turned on by an activated word line, as a result of which the data signal of a selected memory cell can subsequently be read out or written.
For a memory access, usually a plurality of memory cells are read from or written to within an access cycle. By way of example, a number or all of the memory cells along an activated word line are read from or written to. Such a memory access is generally referred to as a so-called burst, and the number of selected memory cells or the number of read-out or writing steps to be executed within an access cycle is referred to as the burst length. At the beginning of the access, a start address is applied to the memory, and the access to the memory cells to be addressed within a burst is controlled internally, without in each case applying a new is address to the memory.
In synchronous memories such as so-called SDRAM (Synchronous Dynamic Random Access Memories) and DDR-DRAM-memories(Double-Data Rate Dynamic Random Access Memories), configuration values of the memory such as, for example, the burst length are programmed in a so-called mode register. To that end, usually by using a correspondingly provided mode register set command, the value for the burst length is written to the mode register via address pins of the memory and is stored in the register for a later memory access. The programming of the mode register thus requires an additional processing step in the operation of the memory.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated memory which overcomes the above-mentioned disadvantages of the prior art apparatus of this general type.
In particular, it is an object of the invention to provide an integrated memory in which the values for configuring the memory can be set with comparatively little outlay.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory, including: a memory cell array having memory cells; and a control circuit for controlling a read memory access for reading out a data signal from one of the memory cells and/or a write memory access for writing a data signal into one of the memory cells. For performing the memory access, the control circuit is designed for receiving an access command that is either an activation command, a read command, or a write command. For performing the memory access, the control circuit is designed for receiving a configuration value in a combined manner with the access command. The configuration value is either a CAS latency value or a value for specifying a burst access.
In accordance with an added feature of the invention, the control circuit is designed to receive a multi-bit signal that includes the access command and the configuration value.
In accordance with an additional feature of the invention, command pins are provided for receiving the access command and for receiving the configuration value. The command pins are connected to the control circuit.
In accordance with a further feature of the invention, the configuration value is the value for specifying the burst access; and the configuration value is either a value for specifying a burst length or a value for specifying a burst type.
In accordance with a further added feature of the invention, there is provided, address pins for transferring address signals for the memory access. The address pins are not capable of transferring the configuration value and are not used for transferring the configuration value.
The control circuit is designed and can be operated in such a way that, for a memory access, a configuration value for specifying a burst access and/or a configuration value for a so-called CAS latency is received in a combined manner with the access command. The access command is received for a memory access by the control circuit in the form of an activation command, a read command or a write command. In the inventive memory, the programming of a mode register can thus be eliminated since the corresponding configuration values can be received with the respective access command and can be set directly. The programming step for the mode register is thus obviated.
This affords the further advantage that the presence of a mode register can be dispensed with, thereby saving space on the memory. Moreover, the respective configuration values can advantageously be altered in each case with the reception of a new access command, without having to perform a renewed programming step for programming a mode register.
The abovementioned CAS latency is employed in synchronous memory modules and indicates at what instant a synchronized data output to outside the memory cell array begins in the event of a read access to one of the memory cells. As a result, in the event of a read access, a data packet is obtained on a bit line at a defined instant. The CAS latency is programmed and set in a manner dependent on the operating frequency of the memory, in order to obtain an optimum data throughput at any operating frequency in the event of a read access to one of the memory cells. To date, the CAS latency has usually been programmed via the mode register set command. Since, according to the invention, this value is transferred together with the access command, is set directly, and can correspondingly be altered with each new access command, higher flexibility at different operating frequencies of the memory is possible.
In one embodiment of the invention, the control circuit is designed and can be operated in such a way that the access command and also the configuration value for the CAS latency and/or the configuration value for specifying a burst access are received with a multi-bit signal. This makes it possible that, with the application of the access command, by way example, the configuration value for specifying the burst length and/or a burst type (for instance sequential read-out or interleaved in a so-called interleave burst) can be transferred in a multi-bit signal.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a integrated memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
REFERENCES:
patent: 6215709 (2001-04-01), Wright et al.
Mayback Gregory L.
Tran M.
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