Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1999-02-02
2001-04-10
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S766000, C714S746000
Reexamination Certificate
active
06216248
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to an integrated memory having an error correction function.
An error correction function for integrated memories (such as dynamic memories, DRAMs) is produced using so-called error correction codes (ECC). In the simplest case, a so-called parity check is carried out. Therefore, for each data word which is to be stored having a number of bits, one or more parity bits are produced and stored in the memory together with the data word. When the data word is read from the memory, the parity bits stored with it are evaluated, as a result of which, depending on the number of parity bits, one or more bit errors can be detected and also corrected, depending on the error correction code used. A simple and widely used error correction code is the Hamming code. Memories equipped with such an error correction function require additional storage space for storing the parity bits.
Hence, there are two types of memories. First, there are memories which are not provided with any error correction function and in which, accordingly, the storage requirement per data word corresponds exactly to the number of bits per data word. Second, there are memories that have an error correction function and have a storage requirement per data word that is increased by the parity bits, but which allow the correction of errors occurring during storage. The former memories are suitable for storing useful data that are insensitive to errors, such as audio data. The latter memories are suitable for applications in which the absence of errors is very important, as is the case of program memories, for example.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated memory that overcomes the above-mentioned disadvantages of the prior art devices of this general type, which has an error correction function and can be optimized for storing data which are sensitive and insensitive to errors.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory, including: a first and a second mode of operation; at least one first memory area for storing useful data in both the first and the second mode of operation; at least one second memory area for storing error correction data associated with the useful data stored in the at least one first memory area during the first mode of operation but not during the second mode of operation; and an error correction unit for producing and evaluating the error correction data stored in the at least one second memory area, the error correction unit activated during the first mode of operation and deactivated during the second mode of operation.
The integrated memory has two modes of operation and at least two memory areas. The first memory area is used to store useful data in both modes of operation. Useful data are the bits of a data word which are to be stored, excluding additional error correction bits or parity bits. The second memory area is used in the first, but not in the second, mode of operation to store error correction data for useful data which are to be stored in the first memory area. In the first mode of operation, the memory thus has an error correction function which assigns error correction data (error correction bits or parity bits), which are to be stored in the second memory area, to the useful data, which are to be stored in the first memory area. In the second mode of operation, the useful data are stored in the first memory area without additional error correction data being stored in the second memory area.
Hence, in the second mode of operation, the error correction function of the memory is deactivated. In the first mode of operation, the memory is therefore suitable for storing useful data for which a high level of error immunity is important, as is the case with program data, for example. In the second mode of operation, the memory is preferably suitable for the type of data for which a high level of error immunity is not important, as is the case with audio data, for example. In terms of obtaining an advantage, the second memory area should be dimensioned such that, in the first mode of operation, it can hold all the error correction data assigned to the useful data in the first memory area. The second memory area will therefore usually be smaller than the first memory area.
The integrated memory according to the invention may, for example, be a DRAM, an SRAM, an EPROM or any other desired type of integrated memory.
The memory also has an error correction unit which is used to produce and evaluate the error correction data which are to be stored in the second memory area. The error correction unit is activated only in the first, but not in the second, mode of operation. Therefore, the error correction unit carries out the error correction function only in the first mode of operation.
According to a first embodiment of the invention, the second mode of operation is an energy-saving mode of operation in which the second memory area is deactivated. In this instance, “deactivated” means that the current consumption of the second memory area is reduced or is even zero. The deactivation is possible because the second memory area is not required for storing error correction data in the second mode of operation. In the second mode of operation, such a memory is suitable for storing data that are not sensitive to errors, while at the same time having lower current consumption than in the first mode of operation. Conventional memories have either no error correction function at all and therefore cannot be used for storing data which are sensitive to errors, or else they have an error correction function which is permanently activated, so that their current consumption is relatively high, even when storing data which are not sensitive to errors and do not require error correction.
According to a second embodiment of the invention, the second memory area is used to store useful data in the second mode of operation, in which it does not store any error correction data. Therefore, in the second mode of operation, useful data can be stored both in the first and in the second memory area. Hence, in the second mode of operation, there is a greater storage capacity available than in the first mode of operation. Consequently, more useful data can be stored in the memory in the second mode of operation than in the first mode of operation, provided that data that are insensitive to errors are being dealt with. In conventional memories with or without an error correction function, the storage capacity is always the same, regardless of whether data that are sensitive or insensitive to errors are to be stored.
Depending on the embodiment, the memory according to the invention thus affords the option either of altering the current consumption of the memory or of having a storage capacity of variable size available, depending on the type of data to be stored or the desirable level of error immunity.
The two memory areas can either be spatially separate from one another, for example by being constituent parts of different memory cell arrays or memory blocks, or they may be disposed concatenated within the same memory cell array or memory block.
According to one development, the memory has a test unit to test the first memory area for storage errors and to define the mode of operation of the memory, depending on the test result. During operation of the memory, the test unit can, for example, test the first memory area and activate the error correction function by changing over from the second to the first mode of operation only if storage errors actually occur.
This has the advantage that, if no storage errors are present, the memory is operated in the second mode of operation, in which, as explained, power consumption can be lower than in the first mode of operation, for example.
Alternatively, a changeover between the modes of operation can also take place by a control signal supplied to the memory externally. The
Mc Connell Roderick
Richter Detlev
Chung Phung M.
Greenberg Laurence A.
Lerner Herbert L.
Siemens Aktiengesellschaft
Stemer Werner H.
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