Electrical computers and digital processing systems: processing – Processing control – Mode switch or change
Reexamination Certificate
2008-01-22
2008-01-22
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Mode switch or change
Reexamination Certificate
active
07321965
ABSTRACT:
A microprocessor includes a core configured to concurrently execute instructions of a plurality of program threads and a yield instruction, included in the instruction set of the microprocessor. The yield instruction includes an opcode for instructing the microprocessor core to suspend issuing instructions of a thread. The thread is one of the plurality of concurrently executed program threads. The yield instruction is an instruction in the thread. The yield instruction also includes a first operand. If the first operand is a first predetermined value the microprocessor core terminates issuing instructions of the thread. If the first operand is a second predetermined value the microprocessor core unconditionally reschedules issuing instructions of the thread. The yield instruction also includes a second operand for receiving a result value of the instruction usable by other instructions of the program thread.
REFERENCES:
patent: 4817051 (1989-03-01), Chang
patent: 4860190 (1989-08-01), Kaneda et al.
patent: 5159686 (1992-10-01), Chastain et al.
patent: 5499349 (1996-03-01), Nikhil et al.
patent: 5511192 (1996-04-01), Shirakihara
patent: 5515538 (1996-05-01), Kleiman
patent: 5659786 (1997-08-01), George et al.
patent: 5758142 (1998-05-01), McFarling et al.
patent: 5812811 (1998-09-01), Dubey et al.
patent: 5867704 (1999-02-01), Tanaka et al.
patent: 5933627 (1999-08-01), Parady
patent: 5944816 (1999-08-01), Dutton et al.
patent: 5949994 (1999-09-01), Dupree et al.
patent: 5961584 (1999-10-01), Wolf
patent: 6061710 (2000-05-01), Eickemeyer et al.
patent: 6088787 (2000-07-01), Predko
patent: 6175916 (2001-01-01), Ginsberg et al.
patent: 6189093 (2001-02-01), Ekner et al.
patent: 6223228 (2001-04-01), Ryan et al.
patent: 6330656 (2001-12-01), Bealkowski et al.
patent: 6330661 (2001-12-01), Torii
patent: 6401155 (2002-06-01), Saville et al.
patent: 6675192 (2004-01-01), Emer et al.
patent: 6687812 (2004-02-01), Shimada
patent: 6697935 (2004-02-01), Borkenhagen et al.
patent: 6877083 (2005-04-01), Arimilli et al.
patent: 6889319 (2005-05-01), Rodgers et al.
patent: 6971103 (2005-11-01), Hokenek et al.
patent: 6986140 (2006-01-01), Brenner et al.
patent: 6993598 (2006-01-01), Pafumi et al.
patent: 7069421 (2006-06-01), Yates, Jr. et al.
patent: 7127561 (2006-10-01), Hill et al.
patent: 7134124 (2006-11-01), Ohsawa et al.
patent: 7185185 (2007-02-01), Joy et al.
patent: 2002/0103847 (2002-08-01), Potash
patent: 2002/0147760 (2002-10-01), Toril
patent: 2003/0014471 (2003-01-01), Ohsawa et al.
patent: 2003/0074545 (2003-04-01), Uhler
patent: 2003/0079094 (2003-04-01), Rajwar et al.
patent: 2003/0115245 (2003-06-01), Fujisawa
patent: 2003/0126416 (2003-07-01), Marr et al.
patent: 2004/0015684 (2004-01-01), Peterson
patent: 2005/0240938 (2005-10-01), Jones et al.
patent: 2007/0106887 (2007-05-01), Kissell
patent: 2007/0106988 (2007-05-01), Kissell
patent: 2007/0106989 (2007-05-01), Kissell
patent: 2007/0106990 (2007-05-01), Kissell
patent: 0725334 (1996-08-01), None
patent: 0917057 (1999-05-01), None
patent: 1089173 (2001-04-01), None
patent: WO0153935 (2001-07-01), None
The Ubicom IP3023™ Wireless Network Processor; “A Next Generation Packet Processor for Wireless Networking”; Apr. 15, 2003; UBICOM, 635 Clyde Ave. Mountain View, CA 94043.
Ungerer et al.; “A Survey of Processors with Explicit Multithreading”; ACM Computing Surveys, vol. 35, No. 1, Mar. 2003, pp. 29-63; Institute of Computer Science, University of Augsberg, Eichleitnerstrasse 30, D-86135 Augsburg, Germany.
David Fotland; A Multithreaded Wireless Network Processor with Software I/O, Embedded Processor Forum, Jun. 18, 2003; www.MDRonline.com.
Intel Technology Journal, vol. 8, issue 01, Feb. 14, 2002, ISSN 1535766X; Hyper-Threading Technology.
Carter et al., “Performance and Programming Experience on the Tera MTA”, Tera Computer Corporation-SIAM Conference on Parallel Processing, Mar. 1999.
Alverson et al., “Tera Hardware-Software Cooperation,” Tera Computer Corporation-Proceedings of the IEEE/ACM SC97 Conference, Nov. 15-21, 1997, San Jose, CA.
“Multithreaded Programming Guide”, SUNSOFT—A Sun Microsystems, Inc, Business; 2550 Mountain View, CA 94043.
Engelschall, R.S., “pth GNU Portable Threads,” Pth Manual, Online! Feb. 17, 2003, pp. 1-31, XP002315713.
Ishihara et al., “A Comparison of Concurrent Programming and Cooperative Multithreading,” Euro-Par 2000 Parallel Processing. 6th International Euro-Par Conference. Proceedings (Lecture Notes in Computer Science vol. 1900) Springer-Verlag Berlin, Germany, Sep. 1, 2000, pp. 729-738, XP002315714, ISBN: 3-540-67956-1.
Frees, W., “Teilzeitarbeit Im Prozessor,” Electronik, Franzis Verlag GMBH. Munche, DE, vol. 45, No. 9, Apr. 30, 1996, pp. 100-106, XP000595386, ISSN: 0013-5658 (English-language version of the search report or action which indicates the degree of relevance found by the foreign office is appended.).
Scheidhauer, Ralf, “Design, Implementierung und Evaluierung einer virtuellen Maschine fur Oz,” Online!, Dec. 1998, Dissertation, Saarbrucken, (English-language version of the search report or action which indicates the degree of relevance found by the foreign office is appended.).
Mehl et al., “An Abstract Machine for Oz,” Research Report RR-95-08, Online!, Jun. 1995, pp. 1-23, Kaiserslautern Saarbrucken, ISSN 0946-008.
Unger et al., “Utilising Parallel Resources By Speculation,” Parallel and Distributed Processing, 1999. PDP '99. Proceedings of the Seventh Euromicro Workshop on Funchal, Portugal Feb. 3-5, 1999, Los Alamitos, CA, USA, IEEE Computing Society, Feb. 3, 1999, pp. 339-343.
Tsai et al: “The Superthreaded Architecture: Thread Pipelining with Run-Time Data Dependence Checking and Control Speculation,” Parallel Architectures and Compiliation Techniques, 1996, Proceedings of the 1996 Conference in Boston, MA, USA, Oct. 20-23, 1996, Los Alamitos, CA, USA, IEEE Comput. Soc., Oct. 20, 1996, pp. 35-46.
Popov, Konstantin: “A Parallel Abstract Machine for the Thread-Based Concurrent Language Oz,” Workshop on Parallism and Implementation of Technology for Constraint Logic Programming Languages, Sep. 1997, pp. 1-25.
Bolychevsky et al. “Dynamic Scheduling in RISC Architectures.” IEEE Proceedings Computers and Digital Techniques, vol. 143, No. 5. Sep. 24, 1996. pp. 309-317.
Marr et al. Hyper-Threading Technology. Intel Technology Journal, Feb. 14, 2002, vol. 6, No. 1, Intel Corporation, USA.
Kissell, Kevin D. “Microprocessor Forum (MPF) Conference Program Presentation: Architectural Extensions to the MIPS Architecture for High-Performance Embedded Systems.” Oct. 15, 2003.
(webpage) Cray MTA-2 Historical Technical Papers, http://www.cray.com/products/programs/mta—2/resources.html. (Mar. 12, 2005). (formerly http://www.cray.com/products/systems/mta/psdocs.html (Jul. 2, 2004)).
Zaslavsky, Leonid et al. “A Scalable Approach for Solving Irregular Sparse Linear Systems on the Tera MTA Multithreaded Parallel Shared-Memory.” Ninth SIAM Conference on Parallel Processing for Scientific Computing, San Antonio, TX. Mar. 1999.
Smith, Burton. “From Here to Petaflops.” Keynote Address, Petaflops-systems Operations Working Review, (POWR), Bodega Bay, California, Jun. 1998.
Briggs, Preston. “Tuning to the BLAS for the Tera.” Workshop on Multithreaded Execution, Architecture and Compilation. (MTEAC 98). Jan. 1998.
Alverson, Gail et al., “Scheduling on the Tera MTA.” IPPS '95 Workshop on Job Scheduling Strategies for Parallel Processing, Santa Barbara, CA, Apr. 1995, and in D.G.Feitelson and L. Rudolph, editors, Job Scheduling Strategies for Parallel Processing, Lecture Notes in Computer Science vol. 949, pp. 19-44, Springer-Verlag 1995.
Smith, Burton. “Folklore and Reality in High Performance Computing Slide Presentation.” 1995.
Smith, Burton. “The Quest for General-Purpose Parallel Comput
Chan Eddie
Davis E. Alan
Huffman James W.
MIPS Technologies Inc.
Petranek Jacob
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