Integrated magnetoresistive semiconductor memory configuration

Details Integrated magnetoresistive semiconductor memory configuration Integrated magnetoresistive semiconductor memory configuration

2003-05-16

2004-08-10

Le, Thong (Department: 2818)

Static information storage and retrieval

Systems using particular element

Magnetoresistive

C365S230060

Reexamination Certificate

active

06775182

ABSTRACT:

BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to an integrated magnetoresistive semiconductor memory configuration, in which n memory cells which each have two magnetoresistive layers, separated by a thin dielectric barrier, and associated word lines and bit lines that cross one another orthogonally are stacked one above the other in n vertical layers. Provision is made of a decoding circuit for selecting one of the n memory layers.
In magnetoresistive memories (MRAMs), the memory effect resides in the magnetically variable electrical resistance of the memory cell.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated magnetoresistive semiconductor memory configuration that overcomes disadvantages of the prior art devices of this general type, which has a cost-effective and practically realizable decoding circuit which can perform a selection from one of the n memory layers disposed vertically one above the other.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated magnetoresistive semiconductor memory configuration. The memory configuration contains n memory cells each having a thin dielectric barrier and two magnetic layers separated by the thin dielectric barrier. Word lines and bit lines are provided, cross one another, and are coupled to the memory cells. The memory cells, the word lines and the bit lines are stacked vertically one above another in n memory layers. A decoding circuit for selecting one of the n memory layers is provided. The decoding circuit, at both ends of one of a respective word line and a respective bit line, in each case has a configuration containing n layer selection transistors connected to and selecting one of the n memory layers and a line selection transistor for selecting one of the word lines and the bit lines to be addressed and to which a voltage is to be applied.
In accordance with a first essential aspect of the invention, the decoding circuit for decoding one of n memory layers, at both ends of a word line or bit line, in each case has a configuration containing n layer selection transistors and a line selection transistor for selecting the word line or the bit line which is to be addressed and to which a voltage is to be applied.
In accordance with another aspect of the invention, which forms a hybrid decoding concept, the decoding circuit has—in the case where the n vertical memory layers point or run in the Z direction, the bit lines point or run in the Y direction and the word lines that cross them orthogonally point or run in the X direction of an imaginary right-angled system of coordinates—at both ends of a word line, an X selection transistor for selecting e.g. a word line, a Z selection transistor for selecting the corresponding memory layer in the Z direction and, furthermore, Y selection transistors for decoding in the Y direction by use of column select lines (for example master word line and segmented WL pieces).
In both of the integrated magnetoresistive semiconductor memory configurations, the transistors that form the decoding circuit are to be implemented at both ends of a word line or bit line. In this case, the source or drain terminals of the layer selection transistors or of the Y selection transistors are connected to one another, and the transistors share a common diffusion region, while the other electrode terminals connect up word or bit lines that are independent of one another. Each transistor of the decoding circuit is configured such that it can drive the high write current of typically 2 mA which is necessary for a memory cell.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated magnetoresistive semiconductor memory configuration, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.


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