Static information storage and retrieval – Systems using particular element – Magnetoresistive
Reexamination Certificate
2001-11-29
2004-06-29
Phan, Trong (Department: 2818)
Static information storage and retrieval
Systems using particular element
Magnetoresistive
C365S171000, C365S173000
Reexamination Certificate
active
06757187
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to an integrated magnetoresistive semiconductor memory and to an associated fabrication method in which each memory cell contains a switching transistor or a diode in the form of an activatable isolating element, and two magnetic layers that are isolated by a thin tunnel barrier. The memory includes connecting conductors that are respectively integrated for word lines, digit lines and bit lines and also for the purpose of activating the switching transistor in one or more memory cells. The connecting conductors are located in a plurality of metallization planes and in a polysilicon connection plane.
Magnetoresistive semiconductor memory cells (MRAM) are based on magnetic memory components which are integrated together with CMOS (Complementary Metal Oxide Semiconductor) components. The main properties of MRAM technology are that the stored data are nonvolatile and that the memory cells permit an unlimited number of read and write access operations.
Ideally, an MRAM cell would be designed without switching elements, i.e. as a pure resistor matrix. However, this has the crucial drawback that parasitic currents flow away via cells which are not being addressed.
Hence, a known MRAM memory cell shown in
FIGS. 1
,
2
A and
2
B uses an activatable MOS transistor to isolate each memory cell and thus achieves a cell structure similar to a DRAM (Dynamic Random Access Semiconductor).
FIG. 1
shows a schematic planar illustration of an exemplary layout for a configuration of 1-transistor MRAM cells.
The actuation for a write and read operation for reading data into and out of an MRAM memory cell is respectively provided by word lines (WL)
1
, WL spur lines
2
, digit lines
3
, and bit lines
5
. The reference numeral
4
denotes an active region (diffusion region),
6
denotes a strap section,
7
denotes a contact between the strap section
6
and the diffusion region
4
, and
8
denotes a minimally attainable cell layout (shown hatched) of
6
F
2
(F signifies the minimum feature size and is shown in
FIG. 1
by the width F of a word line
1
, by way of example).
FIG. 2A
is a schematic illustration of a cross section through an MRAM memory cell as shown in
FIG. 1
, and it can be seen clearly that a stack of two magnetic layers
11
and
12
that are isolated by a thin tunnel barrier
13
form a magnetic tunnel junction structure. The magnetic layer
11
forms a fixed magnetic orientation and the magnetic layer
12
forms a floating magnetic orientation. Depending on the relative polarization of the floating magnetic layer
12
with respect to the fixed magnetic layer
11
, the resistance of the memory cell is either low or high, and the hysteresis when switching between the two states causes the magnetic storage effect.
The MOS switching transistor
15
integrated in the form of an isolating element effects the bit selection for reading individual bits, and as mentioned, ensures that the stored information does not become transitory as a result of parasitic currents via cells that are not being addressed.
FIG. 2A
, and in simplified form,
FIG. 2B
show clearly that the routing of connecting lines, for word lines WL
1
, WL spur
2
, digit line
3
and bit line
5
, requires a polysilicon connection plane GC (Gate Conductor) and three metallization planes M
1
, M
2
and M
3
. M
1
is used, by way of example, to reduce the resistance of the WL (WL spur, WL segmentation), M
2
is required for the digit line DL
3
necessary only for writing, and M
3
is required for the bit line
5
.
It is evident to one of ordinary skill in the art that the large number of metallization and connection planes results in high fabrication costs on account of the complicated process steps required in this regard.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated magnetoresistive semiconductor memory and a method for producing the memory which overcomes the above-mentioned disadvantages of the prior art apparatus and methods of this general type.
In particular, it is an object of the invention to provide a generic magnetoresistive
1
-transistor-cell semiconductor memory and a fabrication method suitable therefore such that the number of metallization planes and hence the process costs are reduced while at the same time the minimum cell layout of
6
F
2
which is achieved in the prior art remains the same. In accordance with one fundamental aspect of the invention, there is provided an integrated magnetoresistive semiconductor memory in which all of the connecting conductors are situated only in two metallization planes and in the polysilicon plane.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated magnetoresistive semiconductor memory that includes a plurality of memory cells. Each one of the plurality of the memory cells includes a thin tunnel barrier, two magnetic layers isolated by the tunnel barrier, and an activatable isolating element consisting of a switching transistor. The memory has integrated connecting conductors including word lines, digit lines, bit lines and at least one line for activating the activatable isolating element of at least one of the plurality of the memory cells. The memory has two metallization planes and a polysilicon connection plane. Each one of the connecting conductors is located in one of the two metallization planes or in the polysilicon connection plane.
In accordance with an added feature of the invention, the digit lines and the low resistance word lines are situated in a given one of the two metallization planes.
In accordance with an additional feature of the invention, the connecting conductors that are located in the polysilicon connection plane serve as a substrate short circuit.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating an integrated magnetoresistive semiconductor memory, that includes steps of: providing an integrated magnetoresistive semiconductor memory including a plurality of memory cells; for each one of the memory cells, providing two magnetic layers that are isolated by a thin tunnel barrier; for each one of the memory cells, providing an activatable isolating element consisting of a switching transistor; providing the integrated magnetoresistive semiconductor memory with integrated connecting conductors including word lines, digit lines, bit lines and lines for activating the activatable isolating element of each one of the plurality of the memory cells; providing each one of the connecting conductors in a plane selected from the group consisting of two metallization planes and a polysilicon connection plane; providing the digit lines in a given one of the metallization planes; providing first lines in the given one of the metallization planes and in the polysilicon connection plane; and using the first lines, which have not yet been used in a layout of the magnetoresistive semiconductor memory, for connecting other elements of the magnetoresistive semiconductor memory.
In accordance with an added mode of the invention, the given one of the metallization planes is used for the low resistance word lines.
In accordance with additional mode of the invention, the polysilicon connection plane is used as a substrate short circuit.
In accordance with one proposed embodiment of the inventive magnetoresistive semiconductor memory architecture, the same metallization plane, namely M
1
, is used both for the digit line and for the low-resistance WL connection. The bit line can then be situated in M
2
.
In another embodiment, the polysilicon connection plane GC is used as a substrate short circuit.
The method for fabricating the integrated magnetoresistive 1-transistor semiconductor memory cell achieves the object described above by inventively using the lines, which have not been used in the layout. These unused lines are situated in the metallization plane for the digit line and in the polysilicon co
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Phan Trong
Stemer Werner H.
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