Integrated logic circuit and hierarchical design method thereof

Details Integrated logic circuit and hierarchical design method thereof Integrated logic circuit and hierarchical design method thereof

2006-12-05

2006-12-05

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07146592

ABSTRACT:
Modules14to18are disposed in a chip10, and the module14includes a plurality of external buffer cells20disposed along the peripheral of the module14, and an internal circuit21disposed inside the plurality of external buffer cells20. Input and output of signals is made between the internal circuit21and the external circuit, through the external buffer cells20. The output-stage transistor of each external buffer cell has a larger size than the transistor size of the internal circuit21. The external buffer cells20have a driving capability for enabling direct driving of a transistor inside the chip through a wire having the maximum Manhattan length of a module-disposed region in on chip. If the disposed area of the plurality of external buffer cells20is not sufficient, the size of the module is enlarged, or repartition is made to reform the modules so that the plurality of external buffer cells20have their sufficient disposed area.

REFERENCES:
patent: 6501301 (2002-12-01), Taguchi
patent: 6567957 (2003-05-01), Chang et al.
patent: 6631508 (2003-10-01), Williams
patent: 6901562 (2005-05-01), Cooke et al.
patent: 62-101047 (1987-05-01), None

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