Integrated logic and latch design with clock gating at...

Details Integrated logic and latch design with clock gating at... Integrated logic and latch design with clock gating at...

2005-07-05

2005-07-05

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S095000, C326S093000

Reexamination Certificate

active

06914453

ABSTRACT:
A method and an apparatus are provided for implementing a logic circuit with integrated logic and latch design. A clock input is provided to the logic circuit. One or more static signal inputs are further provided to the logic circuit. One or more dynamic signal inputs are generated by dynamically gating the one or more static signal inputs with the clock signal. The one or more dynamic signal inputs are applied to the logic circuit, and one or more dynamic signal outputs of the logic circuit are generated. The one or more dynamic signal outputs are precharged, and the one or more dynamic signal outputs are evaluated. The one or more dynamic signal outputs are held when the one or more dynamic signal outputs are neither being precharged nor being evaluated. The one or more dynamic signal outputs are converted into one or more static signal outputs.

REFERENCES:
patent: 5821775 (1998-10-01), Mehta et al.
patent: 6204696 (2001-03-01), Krishnamurthy et al.

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