Patent
1975-12-24
1984-07-10
Larkins, William D.
357 92, H01L 2704, H03K 19091
Patent
active
044596065
ABSTRACT:
The integrated injection logic semiconductor device comprises an N type semiconductor substrate, a P type semiconductor layer laminated on the N type semiconductor substrate, a first N type region extending through the P type semiconductor layer to reach the N type semiconductor substrate, a P type region formed in the first N type region and having a periphery along the outer periphery of the first N type region and a second N type region formed in the P type semiconductor layer. The integrated injection logic semiconductor device is constituted by a PNP lateral transistor utilizing the P type region, the first N type region and the P type semiconductor layer as the emitter, base and collector electrodes respectively, and a NPN vertical transistor utilizing the N type semiconductor substrate, P type semiconductor layer and the second N type region as the emitter, base and collector electrodes, respectively.
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Blatt et al., IEEE IEDM, Dec. 9, 1974, Technical Digest, pp. 511-514.
Ito Shintaro
Nakai Masanori
Nakamura Jun-ichi
Nishi Yoshio
Shinozaki Satoshi
Larkins William D.
Tokyo Shibaura Electric Co. Ltd.
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