Integrated high-performance decoupling capacitor and heat sink

Details Integrated high-performance decoupling capacitor and heat sink Integrated high-performance decoupling capacitor and heat sink

1999-03-31

2001-05-22

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Passive components in ics

C257S537000

Reexamination Certificate

active

06236103

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to semiconductor circuit devices utilizing decoupling capacitors and heat sinks and more particularly to a semiconductor chip having a circuit formed on its active front major surface and having an integral decoupling capacitor and heat sink formed on the inactive back major surface of the chip. Thus, the invention teaches a significant and very effective decoupling capacitor and heat sink combination that, in a single structure provides both a heat sink and a decoupling capacitor in close proximity to the active circuit on the chip requiring either heat sinking or decoupling capacitance or both.
BACKGROUND OF THE INVENTION
As integrated circuits on semiconductor chips became denser, faster and more complex, their electrical performance requirements became higher and the need for greater heat sink capacity became greater. Consequently these integrated circuits required both greater and more effective capacitive decoupling and improved heat sink capacity.
Effective capacitive decoupling in integrated circuits has, in the past, been provided by several different methods. One approach added discrete decoupling capacitors onto the package containing the integrated semiconductor chip. Another approach added the capacitor in available regions in the circuitry itself. The latest approach utilizes the substrate of the chip itself as a capacitive plate with the other plate being comprised of an insulatively coated metallic deposit formed on the back or inactive major surface of the chip.
Each of these approaches have drawbacks. In the first, because the decoupling capacitor is quite remote from the active circuitry on the chip, they provide, at best, only marginal decoupling and no known heat sink capability.
In the second, as the circuitry, on the chip, became denser, the need of larger and better decoupling capacitors that could handle larger on chip voltages or voltage spikes became greater just as the free area into which such capacitors could be placed became reduced. Thus the capacitors became smaller and any heat sinking capacity that they might have provided became similarly reduced.
The latest approach which utilizes the chip substrate as the first plate of the coupling capacitor with the other plate being comprised of an insulatively coated metallic deposit formed on the back or inactive major surface of the chip not only reduced the ability to affix heat sinks onto the chip but the insulation on the surface of the second plate increased the thermal heating effects in the devices on the chip leading to the possibility of reduced electrical performance in the circuitry.
Silicon on insulator (SOI) technology provides enhanced performance by reduction of MOSFET junction capacitance. The power (P) of a semiconductor chip is a function of chip capacitance (C), power supply voltage (V), and the transition frequency (f), i.e., P=CV
2
f. While the decrease in chip capacitance is an advantage for power reduction and enhanced chip performance, the decrease in chip capacitance is a concern for noise, electrostatic discharge, (ESD) and stability. Therefore in silicon on insulator (SOI) devices there is a need for extra capacitance to improve total chip capacitance. This is achieved with decoupling capacitors.
SUMMARY OF THE INVENTION
The present invention solves all of these problems by incorporating in a single component on the chip surface both a heat sink and a decoupling capacitor.
This is achieved by creating a decoupling capacitance that uses the substrate of the chip itself as one of the capacitive plates and a formed metallic deposit that serves as both the second capacitive plate and a heat sink for the active circuit formed on the front or active major surface of the chip.
The present invention thus results in a significant and very effective decoupling capacitor and heat sink combination that, in a single structure provides both a heat sink and a decoupling capacitor in close proximity to an active circuit on an integrated circuit device requiring either heat sinking or decoupling capacitance or both.
More specifically the present invention achieves this desirable result by forming a plurality of trenches in the first plate of the capacitor and placing metal deposits in the trenches and selectively and individually connecting, through appropriate vias, these deposits to the circuits, on the front surface of the chip, needing the precise decoupling capacitance and heat sinking capability.
Accordingly the invention provides, in close proximity to an active semiconductor circuit requiring decoupling capacitance and heat sinking, a significant and very effective decoupling capacitor structure that also serves as a heat sink.
These and other objects and features of the present invention will become further apparent from the following description taken in conjunction with the drawings.


REFERENCES:
patent: 3962713 (1976-06-01), Kendall et al.
patent: 5773362 (1998-06-01), Tonti et al.
patent: 5811868 (1998-09-01), Bertin

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