Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2006-02-16
2008-10-28
Dang, Khanh (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S105000, C714S738000
Reexamination Certificate
active
07444455
ABSTRACT:
A network controller having a multiprotocol bus interface adapter coupled between a communication network and a computer bus, the adapter including a predictive time base generator; and a management bus controller adapted to monitor and manage preselected components coupled with one of the communication network and the computer bus. The management bus controller is adapted to employ an Alert Standard Format (ASF) specification protocol, a System Management Bus (SMBus) specification protocol, an Intelligent Platform Management Interface (IPMI) specification protocol, a Simple Network Management Protocol (SNMP), or a combination thereof. The network controller also includes a 10/100/1000BASE-T IEEE Std. 802.3-compliant transceiver and media access controller coupled with the communication network; a buffer memory coupled with the MAC, wherein the buffer memory includes one of a packet buffer memory, a frame buffer memory, a queue memory, and a combination thereof; and a transmit CPU and a receive CPU coupled with the multiprotocol bus interface adapter and the management bus controller. The network controller can be a single-chip VLSI device in an 0.18 micron CMOS VLSI implementation.
REFERENCES:
patent: 5307354 (1994-04-01), Cramer et al.
patent: 5652530 (1997-07-01), Ashuri
patent: 5761429 (1998-06-01), Thompson
patent: 5815652 (1998-09-01), Ote et al.
patent: 6038689 (2000-03-01), Schmidt et al.
patent: 6065136 (2000-05-01), Kuwabara
patent: 6175927 (2001-01-01), Cromer et al.
patent: 6292831 (2001-09-01), Cheng
patent: 6304900 (2001-10-01), Cromer et al.
patent: 6363071 (2002-03-01), Fink et al.
patent: 6425067 (2002-07-01), Chong et al.
patent: 6477667 (2002-11-01), Levi et al.
patent: 6567937 (2003-05-01), Flores et al.
patent: 6570884 (2003-05-01), Connery et al.
patent: 6754209 (2004-06-01), Stachura et al.
patent: 6772376 (2004-08-01), Merkin et al.
patent: 6829715 (2004-12-01), Chiao et al.
patent: 6915431 (2005-07-01), Vasudevan et al.
patent: 2001/0003526 (2001-06-01), Kanehara
Definition of Gigabit Ethernet by Wikipedia, pp. 1-5, undated.
Definition of Platform Event Trap (PET), IBM.com, pp. 1-2, undated.
Intel® 82546EB Dual Port Gigabit Ethernet Controller Onboard [online], undated.
Distributed Management Task Force, Inc. (DMTF). Specification—DSP0114; Status: Final, copyright 2000, 2001. Alert Standard Format (ASF) Specification, Version 1.03, Jun. 20, 2001, pp. i-v; 2-79.
PCT International Search Report for International Application No. PCT/US02/13151, dated Sep. 4, 2002, (cited in U.S. Appl. No. 10/132,531).
International Search Report, Feb. 28, 2003, 4 pages.
Asker Michael
Hwang Andrew SeungHo
Lindsay Steven B.
Naylor Andrew M.
Broadcom Corporation
Dang Khanh
McAndrews Held & Malloy Ltd.
LandOfFree
Integrated gigabit ethernet PCI-X controller does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated gigabit ethernet PCI-X controller, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated gigabit ethernet PCI-X controller will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4019303