Integrated FET circuit to reduce switching noise

Details Integrated FET circuit to reduce switching noise Integrated FET circuit to reduce switching noise

1987-02-24

1988-12-06

Miller, Stanley D.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307579, 307594, 307596, H03K 17687, H01L 513

Patent

active

047897937

ABSTRACT:
A CMOS output pair provides rapid switching speed while avoiding excessive noise levels developed across the power supply parasitic inductance. Both the P-channel and N-channel transistors of the output pair actually comprise a plurality of sub-transistors with their source to drain current paths connected in parallel. As a result of novel RC coupling of a switching signal from gate to gate of either of the plurality of sub-transistors, the sub-transistors are caused to turn on sequentially. Since none of the sub-transistors is capable of supporting the current that must be carried by the totality of sub-transistors making up either the P-channel or N-channel transistor, the increments of current as each sub-transistor turns on are small relative to the total.

REFERENCES:
patent: 3544962 (1970-12-01), Thompson
patent: 3851185 (1974-11-01), Hatsukano et al.
patent: 4103188 (1978-07-01), Morton
patent: 4335405 (1982-06-01), Sakano et al.
patent: 4509067 (1985-05-01), Minami et al.

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