Integrated ESD structures for use in ESD circuitry

Details Integrated ESD structures for use in ESD circuitry Integrated ESD structures for use in ESD circuitry

1999-06-16

2000-09-12

Ngo, Ngan V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257350, 438155, 438237, H01L 2362, H01L 2701, H01L 2712, H01L 310392

Patent

active

061181552

ABSTRACT:
Apparatus for use in ESD circuitry are provided that comprise a substrate layer on a dielectric wherein the substrate layer includes a first geometric region comprising alternating regions of first and second conductivity types, a second geometric region of substantially one conductivity type surrounding the first geometric region and a third geometric region of substantially one conductivity type surrounding the second geometric region. The substrate layer further includes at least one dielectric layer on at least the second geometric region and a gate layer on the dielectric layer, over the second geometric region and over at least a portion of the second geometric region that is adjacent the alternating first and second conductivity type regions. In a first aspect of the invention, the alternating first and second conductivity type regions preferably are abutted, and a salicide layer may be employed to coupled together adjacent first and second conductivity type regions if desired. In a second and a third aspect of the invention, the alternating first and second conductivity type regions preferably are separated by shallow trench isolation regions or by polysilicon regions, respectively. The at least one dielectric layer may be thicker in at least one portion of the second geometric region than in another portion of the second geometric region. An ASIC book may be formed from one or more of the apparatus.

REFERENCES:
patent: 5485024 (1996-01-01), Reay
patent: 5811857 (1998-09-01), Assaderaghi et al.
patent: 6037636 (2000-03-01), Crippen
S. Voldman et al., "Dynamic threshold body- and gate-coupled SOI ESD protection networks," Journal of Electrostatics 44, pp. 239-255 (1998).

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