Integrated dynamic write-read memory

Details Integrated dynamic write-read memory Integrated dynamic write-read memory

1983-01-17

1986-04-22

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Capacitors

365204, 365189, G11C 700, G11C 1124

Patent

active

045846707

ABSTRACT:
Integrated dynamic write-read memory having a matrix formed of mutually identical memory cells based on MOS technology, the respective memory cells, in turn, being formed of a series arrangement of a transfer transistor and a storage capacitance, the memory cells belonging to individual columns of the matrix being connected, respectively, by a free current-carrying terminal of the transfer transistor thereof to a bit line assigned to the appertaining matrix column and being connected, respectively, by a free terminal of the storage capacitance thereof to a common fixed potential of the memory, comprising means for feeding a voltage, which causes discharge of the storage capacitance of the individual memory cells, across at least one pulsed circuit component of the matrix, for assisting in discharging the storage capacitance during an analysis of information stored in the individual memory cells.

REFERENCES:
patent: 3986180 (1976-10-01), Cade
patent: 4380803 (1983-04-01), Tuan
patent: 4413330 (1983-11-01), Chao et al.
patent: 4477886 (1984-10-01), Au
Fujishima et al., "A Storage Node Boosted RAM with Word Line Delay Compensation", IEEE ISSCC Digest of Technical Papers, Feb. 10, 1982, pp. 66-67.
Stein et al., "Storage Array and Sense/Refresh Circuit for Single Transistor Memory Cells", IEEE Journal of Solid State Circuits, vol. SC-7, No. 5. Oct. 1972, pp. 336-340.

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