Integrated dynamic semiconductor memory with complementary circu

Details Integrated dynamic semiconductor memory with complementary circu Integrated dynamic semiconductor memory with complementary circu

1985-07-01

1988-08-09

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Semiconductive

365203, 365230, G11C 800, H03K 19094

Patent

active

047633018

ABSTRACT:
An integrated circuit for a dynamic semiconductor random access memory, constructed of complementary transistors, has memory cells connected to bit lines by way of individual selection transistors of a first channel type, the operation of which is controlled by word lines. The voltage on the word lines is controlled by a first switching transistor of a second channel type, controlled by the output of a decoder. The first switching transistor is connected between the word line and a selection voltage which alternates between two voltage values of different operational signs, and the gate of the first switching transistor is connected through a capacitor to the selection voltage and through a second switching transistor having its gate at reference potential, to the output of the decoder.

REFERENCES:
patent: 4051388 (1977-09-01), Inukai
patent: 4145622 (1979-03-01), Hofmann et al.
patent: 4267464 (1981-05-01), Takemae et al.
patent: 4389714 (1983-06-01), Nakao
patent: 4618784 (1986-10-01), Chappell et al.
IEEE Transactions on Electron Devices, vol. ED-29, No. 4, Apr. 1982, "An n-Well CMOS Dynamic RAM", pp. 714-718.

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