Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2005-09-06
2005-09-06
Auduong, Gene N. (Department: 2827)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S211000
Reexamination Certificate
active
06940775
ABSTRACT:
An integrated dynamic memory includes memory cells which are combined to form individual independently addressable units, and a control circuit for controlling a refresh mode for the memory cells. The memory cells can have their memory cell content refreshed. The control circuit is designed such that one or more units of memory cells can be subject to a refresh mode in parallel in a refresh cycle. The control circuit sets a number of memory cell units, which are to be refreshed in parallel in a refresh cycle based on a temperature reference value. A maximum possible operating temperature for a memory chip can be increased without additional restrictions on memory access.
REFERENCES:
patent: 5532968 (1996-07-01), Lee
patent: 6084812 (2000-07-01), Joo
patent: 6438057 (2002-08-01), Ruckerbauer
patent: 6809980 (2004-10-01), Schnabel et al.
Eggers Georg Erhard
Kliewer Jörg
Pröll Manfred
Schneider Ralf
Auduong Gene N.
Edell Shapiro & Finnan LLC
Infineon - Technologies AG
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