Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2002-07-26
2004-05-04
Phung, Anh (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S222000, C365S200000
Reexamination Certificate
active
06731552
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to an integrated dynamic memory having a memory cell array with memory cells for storing a charge corresponding to an information bit. The invention further relates to a method for operating an integrated memory of this type.
Integrated memories, such as, for example, a dynamic random access memory (DRAM) use capacitors for storing charge. The charge state in the capacitor in each case represents an information bit.
A DRAM chip contains a matrix of memory cells that are arranged in rows and columns and that are addressed by word lines and bit lines. Reading data from the memory cells or writing data to the memory cells is realized by activating suitable word lines and bit lines.
The charge stored in the capacitor decreases over time on account of recombination and leakage currents. Before the charge has decreased to an indeterminate level below a specific threshold value, the capacitor charge must be refreshed. This operation is referred to as “refresh”. For this reason, these memory cells are called dynamic RAM (DRAM), in contrast to static RAMs (SRAM), which do not need refreshing.
The term retention time refers to that period of time for which a memory cell of a DRAM can retain the stored charge without falling below the threshold value. The refresh time, specifically the time between two refresh operations, must therefore be equal to or shorter than the retention time so that data losses do not occur.
The refreshing of the storage capacitors is generally controlled by an external module, for instance, the controller of a PC (Personal Computer) for all of the installed memory modules. If the memory modules have different refresh times, the weakest module with the shortest refresh time determines the refresh cycle for all of the modules. A refresh that is as infrequent as possible, that is to say a long refresh time, is advantageous since first the memory module is blocked during the refresh and is not available for other tasks, and second every refresh is associated with a charge transport and thus a current consumption. This has a disadvantageous effect particularly in the case of portable devices, whose rechargeable-battery operating time is critical.
A general problem in the case of the retention time of a semiconductor memory is due to the fact that the retention time is not an invariable constant, but rather can depend on the ambient and operating temperature, and also on the age of the module.
At the present time, this circumstance is taken into account by assuming a maximum operating temperature, for example 95°, which is composed for instance of a maximum specified external temperature of 70° C. and an inherent heating proportion of 25° C. The memory modules are then tested at this temperature and memory cells which did not satisfy the specification are replaced by redundant memory cells, or the refresh time is set so conservatively at delivery that the remaining memory cells have a retention time above the chosen refresh time up to the maximum temperature.
For a 128 Mbit memory module having 4096 rows, 64 ms, for example, is generally chosen as the refresh time. The chip is tested at the maximum operating temperature at 64 ms and the weak cells are eliminated in a customary manner by redundancy repairs. After a successful test of a module, it is then assumed that:
the retention time was set correctly by fuses/trimmer;
the retention is identical for volatile logic ones (“1”) and logic zeros (“0”);
the defective cells have been eliminated by redundancy activation;
the inherent chip heating does not increase in operation throughout the lifetime of the product;
the retention susceptibility does not increase or vary with respect to time, as in the case of the so-called “variable retention time”;
the actually tested temperature at which the retention time was determined is known precisely.
These expectations for the most part represent simplified assumptions which, when not completely applicable, are compensated for, for example, by overtesting after production. Alternatively, these assumptions can lead to failures after a certain operating duration. This loss is unacceptable in particular in the case of high-reliability components, for example, in mainframe computers, in power station control and the like.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated dynamic memory which overcomes the above-mentioned disadvantages of the prior art apparatus of this general type.
In particular, it is an object of the invention to provide an integrated dynamic memory that when compared with conventional dynamic memories, has a small current consumption and/or is available for random read/write accesses for the longest possible proportion of time.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated dynamic memory including a memory cell array having a regular cell area with regular memory cells, a first test cell area with first test cells, and a second test cell area with second test cells. The regular memory cells, the first test cells and the second test cells are for storing a charge corresponding to an information bit. The integrated dynamic memory also includes: a control unit for refreshing charge contents of the regular memory cells with a first refresh time T
ref
; a control unit for refreshing charge contents of the first test cells with a second refresh time T1, and for refreshing charge contents of the second test cells with a third refresh time T2; and an evaluation unit for detecting memory cell defects in the first test cell area and in the second test cell area. The first refresh time T
ref
is shorter than the second refresh time T1; and the second refresh time T1 is shorter than the third refresh time T2.
The invention is thus based on the concept of functionally separating subareas of the memory cell array from the regular memory area and using them for monitoring and analyzing the retention time that is presently required. In this case, the invention assumes that the cells used for the retention analysis have the same production-dictated retention quality as the regular memory cell array and the underlying statistics are not significantly impaired by the limited number of cells used for the analysis.
Both assumptions are generally satisfied well, since the cell areas used for the retention analysis originate from the same memory cell array as the regular memory cells. Moreover, after the redundancy activation, there are generally still sufficiently many redundant memory cells available which can be utilized for the retention analysis with adequate statistics.
Preferably, the evaluation unit has a device for altering the refresh times T
ref
, T1 and T2 on the basis of detected memory cell defects. This makes it possible to adapt the refresh time T
ref
to instantaneous conditions depending on the result of the memory tests carried out on the test cell areas, that is to say to increase or decrease the refresh time T
ref
. In this case, operation is carried out with a longer refresh time T1 in the first test cell area, and operation is carried out with an even longer refresh time T2 in the second test cell area.
If the evaluation of the memory test reveals that no memory cell defects occurred even at the longer refresh times T1 and T2, it can be concluded that the present operating conditions according to the temperature and the age of the module also permit the regular memory cells to be used with a longer refresh time T
ref
than presently set.
The refresh times T
ref
, T1 and T2 are expediently chosen such that the refresh time T1 is twice as long as T
ref
, and the refresh time T2 is twice as long as T1. The refresh time of the first test cell area thus differs by the factor
2
, and that of the second test cell area by the factor
4
, from the present setting for the regular memory areas.
This enables a reliable assessment of the appropriate refresh rate: this is because if the first mem
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Phung Anh
Stemer Werner H.
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