Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2002-06-28
2004-04-13
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000
Reexamination Certificate
active
06721215
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to an integrated dynamic memory having a memory cell array having memory cells. The invention further relates to a method for operating such an integrated dynamic memory.
The memory area and the capacity of Dynamic Random Access Memory (DRAM) Chip modules are fixedly predetermined. This makes it necessary, in order to increase the yield in chip production, to take measures that ensure the predetermined storage capacity is reached.
To such an end, it is customary to provide on the memory modules a number of redundant memory cells that can replace a certain number of defective regular memory cells.
The memory modules are generally tested for functionality by the manufacturers before their delivery, and, as far as possible, are repaired. Such repair is done, for example, as follows: after chip production, memory defects are determined by targeted testing and recorded in a defect log. Then, by programmable elements, for example, a series of so-called laser fuses, individual word lines or bit lines containing defective memory cells are exchanged, in address terms, for defect-free redundant word lines or bit lines.
Such a redundancy concept makes it possible to increase the chip yield during fabrication. It has the disadvantage, however, that a certain proportion of redundant memory cells has to be provided. In such a case, it can happen, on one hand, that, for instance, in a well settled production process, only a small number of defective memory cells occur, so that the chip area used for the redundant memory area is taken up unnecessarily. If, on the other hand, the proportion of redundant memory cells is too small, the memory module as a whole can no longer be utilized and must be rejected.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated dynamic memory and method for operating it that overcome the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that provides an integrated dynamic memory having improved utilization of the regular memory area.
With the foregoing and other objects in view, there is provided, in accordance with the invention, an integrated dynamic memory, including a memory cell array having memory cells, each of the memory cells assigned to one of a plurality of cell groups, the plurality of cell groups divided into defect-free groups having exclusively defect-free memory cells and defective groups having at least one defective memory cell, a memory configuration table connected to the memory cell array and adapted to contain a list identifying the defect-free groups, and an assignment unit connected to the memory configuration table, the assignment unit programmed to execute memory accesses only to the memory cells of the defect-free groups based upon the list in the memory configuration table.
The invention is, thus, based on the concept of addressing the available memory area of the integrated memory by indirect addressing through an assignment unit. To that end, the memory area is firstly subdivided into groups of suitable size.
The size chosen for the groups results from weighing up the management complexity for the organization and storage of the groups (preferably large groups with little complexity) and the loss of defect-free memory area in the event of the entire group being rejected due to a defective memory cell (preferably small groups with little loss).
After a test of the memory cells, which test can be carried out while the memory cells are still with the manufacturer or, alternatively, not until the memory cells are with the customer, those groups that contain exclusively defect-free memory cells are entered into a memory configuration table. An assignment unit then carries out the memory accesses according to the entries in the memory configuration table, that is to say, accesses only memory cells of defect-free groups.
The total memory area results from stringing together the memory cells of the defect-free groups. Consequently, the total capacity of the memory module also need not be defined once and for all with fabrication. Rather, the capacity may result only after a memory test, or may even vary in the course of the module lifetime, without the module ever having to be rejected as a whole.
In accordance with another feature of the invention, the memory cell array of the integrated dynamic memory has a plurality of word lines and a plurality of bit lines, memory cells respectively being disposed at the crossover point between a word line and a bit line.
In accordance with a further feature of the invention, each of the plurality of groups contains the same number of memory cells. This configures the management of the groups and the capacity calculation in a particularly simple manner.
In accordance with an added feature of the invention, the groups of memory cells are organized such that each of the plurality of groups contains at least one word line. In such a case, it has proved to be particularly advantageous if each of the plurality of groups contains exactly one word line. In that case, on one hand, ascertaining a defect within a group and the management of the defect-free groups is simple and uncomplicated and, on the other hand, not an excessively large amount of memory space is given away by virtue of the entire group being removed from the list of the defect-free groups in the event of a single defective memory cell.
In accordance with an additional feature of the invention, in the integrated dynamic memory, the assignment of the memory cells to the groups is defined once, and the list of the defect-free groups is stored in a permanent manner in the memory configuration table. The single definition of the assignment then typically takes place after production whilst still with the manufacturer. However, it also lies within the scope of the invention not to define and store the assignment until later, possibly not until with the customer.
In accordance with yet another feature of the invention, in the integrated dynamic memory, the assignment of the memory cells to the groups is defined repeatedly, and the list of the defect-free groups is stored in an overwriteable manner in the memory configuration table.
To such an end, in accordance with yet a further feature of the invention, the integrated dynamic memory may advantageously have a self-test unit for functional testing of the memory cells, which, during operation, in response to a request signal, tests the memory cells of the memory cell array for defectiveness and which interacts with the assignment unit such that the assignment unit stores a list of the defect-free groups in the memory configuration table in an overwriteable manner. Such a request signal may be generated, for instance, during every boot operation of the computer into which the memory module is incorporated.
In such a refinement, the storage capacity of the module is not necessarily fixed for the entire lifetime, rather it may slowly decrease over the course of time as a result of increasingly occurring cell defects, without the memory module ever becoming non-functional as a whole.
In accordance with yet an added feature of the invention, the total capacity of the memory cells associated with the defect-free groups is entered in a readable register. This information is then available during the system start-up by a simple read-out operation.
With the objects of the invention in view, there is also provided a method for operating an integrated dynamic memory having a memory configuration table and a memory cell array with memory cells, including the steps of assigning each of the memory cells to one of a plurality of groups, testing the memory cells for functionality once, entering into the memory configuration table each of the groups having exclusively defect-free memory cells, and during further operation, executing memory accesses only to memory cells assigned to a defect-free group entered into the memory configuration table.
Le Thoai-Thai
Lindolf Jürgen
Greenberg Laurence A.
Hoang Huan
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
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