Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
1999-11-03
2001-11-06
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S543000
Reexamination Certificate
active
06313670
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a packet-type semiconductor memory device, and more particularly, to a current control circuit for controlling the current driving capability of an output driver in a packet-type semiconductor memory device.
2. Description of the Related Art
Recently, semiconductor memory devices which receive data and addresses in units of a packet, such as, RamBus DRAMs, have been put into use to achieve high-speed operation of semiconductor memory devices. In a system adopting the packet-type semiconductor memory device, as shown in
FIG. 1
, a memory controller
109
and a plurality of memory devices
101
through
108
are commonly connected to signal lines B
1
through Bn which are typically called channels. Thus, the packettype semiconductor memory device includes a current control circuit for finely controlling the current driving capability of an output driver according to the size of a load which is applied to a pad.
FIG. 2
is a circuit diagram of a packet-type semiconductor memory device including a conventional current control circuit. Here, only circuits associated with the current control of an output driver are shown.
Referring to
FIG. 2
, the semiconductor memory device includes first and second pads P
21
and P
22
, an output driver O
21
, a current control circuit CT
21
, and a control circuit L
21
. The conventional current control circuit CT
21
includes first and second transfer gates T
21
and T
22
, a voltage divider, a comparator C
21
, and a current control counter D
21
. The first transfer gate T
21
transfers the voltage of the first pad P
21
, that is, an output high voltage (VOH) in response to a current control enable signal CCTG. The second transfer gate T
22
transfers the voltage of the second pad P
22
, that is, an output low voltage (VOL) in response to the current control enable signal CCTG. The voltage divider includes resistors R
21
and R
22
, and divides a voltage ranging between the outputs of the first and second transfer gates T
21
and T
22
and outputs a divided voltage Vcmp. The comparator C
21
compares the divided voltage Vcmp with the reference voltage Vref. The current control counter D
21
generates control bits ICTRO through ICTR
5
for controlling the current driving capability of the output driver O
21
in response to the output of the comparator C
21
.
However, in the conventional current control circuit CT
21
, when the absolute values of the resistances of the resistors R
21
and R
22
of the voltage divider are made small to quickly bring the divided voltage Vcmp to a steady state, an increased amount of current flows through the resistor R
21
and R
22
, so that the levels of the output high voltage VOH and output low voltage VOL are changed. Accordingly, the divided voltage Vcmp becomes different from an original target value, that is, (VOH+VOL)/2. However, when the amount of current flowing through the resistors R
21
and R
22
is reduced by increasing the absolute values of the resistances of the resistors R
21
and R
22
to prevent such a problem, the amount of time taken for the divided voltage Vcmp to reach a steady state greatly increases.
Also, the conventional current control circuit CT
21
uses transfer gates as transfer means for transferring the voltage VOH of the first pad and the voltage VOL of the second pad, such that the divided voltage Vcmp is different from an original target value even if the effective resistances of the first and second transfer gates T
21
and T
22
become different from each other due to factors such as a change in the manufacturing process, a change in temperature, or the like.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a current control circuit which can minimize variations in an output high voltage (VOH) and an output low voltage (VOL) and quickly and accurately bring a divided voltage to a steady state, in a packet-type semiconductor memory device.
Another object of the present invention is to provide a packet-type semiconductor memory device including a current control circuit which can minimize variations in an output high voltage (VOH) and an output low voltage (VOL) and quickly and accurately bring a divided voltage to a steady state.
Accordingly, to achieve the first object of the present invention, there is provided a current control circuit including: a first transfer means for transmitting the voltage of a first pad in response to a current control enable signal; and a second transfer means for transmitting the voltage of a second pad in response to the current control enable signal. The first and second transfer means are buffers.
The current control circuit further includes a voltage divider, a comparator, and a current control counter. The voltage divider divides a voltage ranging between the voltage outputs of the first and second transfer means and outputting the divided voltage. The comparator compares the divided voltage with a reference voltage. The current control counter generates control bits for controlling the current driving capability of the output driver, in response to the output of the comparator.
It is preferable that the buffer is a differential amplification type buffer, and that the voltage divider is a current mirror type voltage divider. The voltage divider can be a resistor ladder type voltage divider.
To achieve the second object of the present invention, there is provided a semiconductor memory device including: first and second pads; an output driver connected to the second pad, for driving the second pad; and a current control circuit for controlling the current driving capability of the output driver. The current control circuit includes: a first buffer for transmitting the voltage of the first pad in response to a current control enable signal; a second buffer for transmitting the voltage of the second pad in response to the current control enable signal; a voltage divider Tor dividing a voltage ranging between the voltage outputs of the first and second buffers and outputting a divided voltage; a comparator for comparing the divided voltage with a reference voltage; and a current control counter for generating control bits for controlling the current driving capability of the output driver, in response to the output of the comparator.
It is preferable that the first and second buffers are differential amplification type buffers, and that the voltage divider is a current mirror type voltage divider. The voltage divider can be a typical resistor ladder type voltage divider.
REFERENCES:
patent: 3988691 (1976-10-01), Shih
patent: 4481625 (1984-11-01), Roberts et al.
patent: 4941153 (1990-07-01), Kelley et al.
patent: 5194765 (1993-03-01), Dunlop et al.
patent: 5254883 (1993-10-01), Horowitz et al.
patent: 5424662 (1995-06-01), Bonaccio
patent: 5450026 (1995-09-01), Morano
patent: 5818269 (1998-10-01), Brown et al.
patent: 5880599 (1999-03-01), Bruno
patent: 5917349 (1999-06-01), Nguyen
patent: 5920204 (1999-07-01), Bruno
patent: 5939926 (1999-08-01), Uber
patent: 6094075 (2000-07-01), Garrett, Jr. et al.
Park Chan-Jong
Song Ki-Whan
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
Tran Toan
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