Integrated DRAM memory cell and DRAM memory

Details Integrated DRAM memory cell and DRAM memory Integrated DRAM memory cell and DRAM memory

2001-03-09

2002-09-03

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S051000, C365S063000

Reexamination Certificate

active

06445609

ABSTRACT:

The present invention firstly relates to an integrated DRAM memory cell according to the precharacterizing clause of claim
1
. The invention also relates to a DRAM memory.
DRAM (Dynamic Random Access Memory) memory cells and memories represent an important type of memory for storing digital information. A DRAM is a memory in which data can be stored after inputting an address and can be read out again under this address. In DRAM memory cells or memories, respectively, the information is not stored as a switching state of a circuit but as a charge quantity in a capacitance. Such a memory cell can thus be formed with only one storage capacitor and one selection transistor. An example of a DRAM memory cell is shown in FIG.
1
. Since each capacitor has leakage currents and leakage currents also flow via the selection transistor, the information in the DRAM memory cell is continuously reduced. The information content of the memory cell is therefore lost with time. In order to avoid this, the contents of the memory cells are periodically read out, the memory contents are evaluated and the memory cell is written to again. This means that the charge contents of the storage capacitors are refreshed again.
DRAM memory cells are usually connected together to form memory cell arrays, a DRAM memory having one or more such memory cell arrays. As a rule, only a limited area, which is called cell area and has an essentially rectangular configuration, is available to form the individual memory cell components (storage capacitor and selection transistors. The cell area usually has a greater extent in the longitudinal direction (longitudinal extent) than in the width direction (lateral extent). The individual components of the memory cell or, respectively, of its individual component parts are, as a rule, arranged approximately in a line and at a certain distance from one another behind one another within the boundary of the cell area. The resultant extent of the memory cell and thus also of the cell area is understood to be the longitudinal extent or extent in the longitudinal direction, respectively. The resultant extent of the memory cell in the perpendicular direction thereto, and thus also of the cell area, is understood to be the lateral extent or, respectively, extent in the lateral direction. Each memory cell is wired or can be wired to the cell periphery via a word line and a bit line, the word line and the bit line being conducted over the memory cell and being at least essentially oriented perpendicularly to one another. Such a configuration of the memory cell is shown by way of example in FIG.
1
. By activating a certain word line, all memory cells connected to it can be read out, written to or refreshed with respect to their information content via their bit lines.
An essential feature of the DRAM development is the miniaturization of the patterns. On the one hand, the minimum pattern size F to be generated lithographically is reduced in size approximately by a factor of 1/{square root over (2)} from generation to generation. On the other hand, the architecture of the memory cell is changed in such a manner that the consumption of area per bit drops.
The bit line wiring of the individual cells establishes a grid into which read/write amplifiers also have to be introduced. The basic task of read/write amplifiers is to evaluate and amplify signals read our of the bit lines.
The area needed for the total wiring per memory cell defines a minimum size for the cell area up to which a reduction in size of the memory cell architecture leads to a saving in area. Dropping below this minimum cell size would mean that the space requirement of such wiring is fixed by the wiring grid and thus independent of the cell size achieved or achievable.
In the so-called “folded” bit line architecture hitherto used as is shown, for example, in FIG.
4
and will be explained in greater detail in the description of the figures, the minimum area needed for the wiring per cell is 8 F
2
. This can also be seen, for example, in FIG.
2
. In the “folded” bit line concept, the individual bit lines are in each case arranged next to one another. This requires two bit lines in each case, namely a bit line BL to be evaluated and a reference bit line BBL. The reference bit line BBL has the task of comparing a signal read out of the bit line or, respectively, memory cell to be evaluated, with a reference value. This will be explained by means of a brief example.
In the DRAM memory cells, digital information can be stored, for example, in the form of logical “0” and “1”. To each of these logical information items, a certain voltage value is allocated. For example, the voltage value for a logical “0” can be zero volts, whereas the voltage value for a logical “1” is, for example, 2 volts. Before the memory cell is read out, a reference voltage is applied to all bit lines, for example a voltage of 1 volt. When the memory cell is read out, the voltage value will either increase or decrease, depending on the information content of the memory cell. This change in voltage is compared with the reference voltage of 1 volt which is still present in the reference bit line. If the voltage value in the bit line to be evaluated is higher than the reference voltage value, the information content logical “1” was written in the memory cell. If the voltage values are smaller, the information logical “0” was written in the memory cell. The voltage signal read out of the bit line to be evaluated and of the reference bit line is conditioned and processed further, for example amplified in the read/write amplifier.
In the “folded” bit line concept, two word lines WL are conducted over each memory cell. One word line activates the selected cell whilst leaving the neighbouring cells, and thus the neighbouring bit line, deactivated. The second word line only passes the cell to be read out and activates the neighbouring cells when selected. A wiring architecture comprising one bit line BL and two word lines WL conducted in parallel over the memory cell needs an area of at least 8 F
2
as shown in FIG.
2
. The “folded” bit line concept is thus only appropriate for cells ≧8 F
2
.
Above the 4-Gbit generation, the architecture of the DRAM memory cell requires an area consumption of less than 8 F
2
. The wiring must then be changed in such a manner that it does not determine the space requirement of the cell array. This is achieved by conducting only a single word line over each cell. This is shown, for example, in FIG.
3
. As can be seen from this figure, the minimum space requirement for the wiring drops to 4 F
2
. The consequence for the bit line architecture is a transition from the “folded” to the so-called “open” bit line concept. Such an “open” concept is shown, for example, in FIG.
5
and will be explained in greater detail in the description of the figures. As can be seen from
FIG. 5
, the grid of the read/write amplifier SA is reduced from 8 F to 4 F with a conventional word line and bit line arrangement, independently of the size of the memory cell. The grid is reduced abruptly which means that this grid is required for each cell which is <8 F
2
regardless of whether it is a 7 F
2
, 6 F
2
, 4 F
2
cell or the like.
As can be seen from
FIGS. 4 and 5
, the grid of the read/write amplifier (SA grid) is determined by, among other things, the width of the bit line BL, the distance between the bit lines and by the arrangement of bit line BL and reference bit line BBL.
For cells <8 F
2
, only a single word line WL can be supplied per cell. As a consequence of this, the neighbouring cells are also read out and the neighbouring bit line cannot be used as reference bit line as was possible in the “folded” bit line concept shown in FIG.
4
. Instead, a bit line BBL from a neighbouring cell array is used as reference bit line. This results in the “open” bit line concept and the SA grid is abruptly reduced from 8 F to 4 F independently of the cell size.
In conventional bit line architectures, the distance between adjacent bit lines res

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