Integrated die bumping process

Details Integrated die bumping process Integrated die bumping process

2008-07-15

2008-07-15

Le, Thao P. (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C257SE21508

Reexamination Certificate

active

07399695

ABSTRACT:
An integrated die bumping process includes providing a load board, defining a plurality of die regions on a surface of the load board for placing dice of a plurality of die specifications, affixing a plurality of dice respectively on the die regions according to the plurality of die specifications, and performing a die bumping process.

REFERENCES:
patent: 6537831 (2003-03-01), Kline
patent: 6639324 (2003-10-01), Chien
patent: 6864116 (2005-03-01), Kim et al.
patent: 6869809 (2005-03-01), Yu et al.
patent: 6919508 (2005-07-01), Forcier
patent: 6921716 (2005-07-01), Huang et al.
patent: 7038287 (2006-05-01), Kim et al.
patent: 7061122 (2006-06-01), Kim et al.
patent: 7061123 (2006-06-01), Chee et al.
patent: 7081404 (2006-07-01), Jan et al.
patent: 2002/0190369 (2002-12-01), Hikita et al.
patent: 2003/0030137 (2003-02-01), Hashimoto
patent: 2003/0057563 (2003-03-01), Nathan et al.
patent: 2003/0203539 (2003-10-01), Islam et al.
patent: 2004/0250229 (2004-12-01), Tran
patent: 2005/0191836 (2005-09-01), Tzeng et al.
patent: 2005/0269687 (2005-12-01), Forcier
patent: 2005/0274003 (2005-12-01), Lee
patent: 2006/0063311 (2006-03-01), Ho et al.

Affiliated with

Also associated with

Rating

Integrated die bumping process does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated die bumping process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated die bumping process will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2810069