Integrated device with multiple reading and/or writing commands

Details Integrated device with multiple reading and/or writing commands Integrated device with multiple reading and/or writing commands

2008-05-20

2008-05-20

Portka, Gary (Department: 2188)

Electrical computers and digital processing systems: memory

Address formation

Address multiplexing or address bus manipulation

C710S004000, C710S074000, C711S001000, C711S103000, C711S220000

Reexamination Certificate

active

07376810

ABSTRACT:
An integrated device is provided that includes a non-volatile memory having an addressing parallelism and a data parallelism, and a communication interface for interfacing the memory with an external bus. The external bus has a transfer parallelism lower than the addressing parallelism and the data parallelism. The communication interface includes control means for executing multiple reading operations and/or multiple writing operations on the memory according to different modalities in response to corresponding command codes received from the external bus. Also provided is a method of operating such an integrated device.

REFERENCES:
patent: 6327632 (2001-12-01), Sollars
patent: 6735661 (2004-05-01), Gelke et al.
patent: 6944093 (2005-09-01), Sumitani

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