Integrated device having MOS transistors which enable positive a

Details Integrated device having MOS transistors which enable positive a Integrated device having MOS transistors which enable positive a

1993-07-12

1994-06-14

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257546, 257357, 3072962, H01L 2702, H03K 301

Patent

active

053212932

ABSTRACT:
A semiconductor circuit integrated with CMOS circuits for receiving a TTL input voltage and generating a large negative and positive voltage swing with respect to p-type or n-type substrate is disclosed. This invention is based on elimination of the electro-static discharge (ESD) protection circuit which is a requirement for any integrated circuit. Eliminating the ESD protection circuit also eliminates the clamping feature of the ESD protection circuit and therefore the circuit can be driven to negative voltages for PMOS circuits and to positive voltages for NMOS circuits. This provides the possibility of connecting the drain of a a P-channel type metal oxide silicon field effect (PMOS) transistor, which is fabricated on a p-type substrate within an n-well, to a voltage below the the substrate voltage. Also, in a n-channel type metal oxide silicon field effect (NMOS) transistor which is fabricated on a n-type substrate within a P-well, the drain can be connected to voltages higher than the substrate voltage. Utilizing this feature of a MOS transistor provides a way to design an integrated circuit which can handle negative voltage swings as well as positive voltage swings.

REFERENCES:
patent: 5124778 (1992-06-01), Adachi
patent: 5182469 (1993-01-01), Farley et al.

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