Integrated design verification and design simplification system

Details Integrated design verification and design simplification system Integrated design verification and design simplification system

2006-01-03

2006-01-03

Whitmore, Stacy A. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06983435

ABSTRACT:
A design model verification method includes performing under approximation (UAV) processing to potentially resolve a defined verification problem and to identify a set of reachable states for the design model. If UAV processing fails to resolve the defined verification problem, coverage data extracted from the UAV processing is evaluated to identify new candidates for design model simplification and to disprove previously identified simplification candidates. Over approximation verification (OAV) processing is performed to potentially resolve the verification problem and to prove one or more previously identified simplification candidates. If the OAV processing fails to resolve the verification problem, the design model is simplified using any proven simplification candidates and any states that disproved a previously identified simplification candidate are stored to use a seed state for subsequent UAV processing.

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