Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-06-14
2005-06-14
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C703S014000
Reexamination Certificate
active
06907586
ABSTRACT:
A system, method and program product for designing integrated circuits. A design of an integrated circuit (IC) is analyzed to identify the longest path between each pair of registers. A crosstalk overhead is calculated for each identified longest path using a stochastic model. The crosstalk overhead of each longest path is added to selected path delays as an incremental port of register set up time. Any path wherein the sum of the path delay and crosstalk overhead exceeds a maximum accepted delay, i.e., where slack is less than or equal to zero is redesigned and the IC is then, placed and wired. The stochastic model may be a tree-like structure derived from several completed integrated circuit (IC) designs, in particular from cell placement and wiring for the completed IC. The tree-like stochastic model corresponds crosstalk delays to technology wire factors.
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Al-Dabagh Maad A.
Huang Tammy T.
Tetelbaum Alexander
Fitch Even Tabin & Flannery
LSI Logic Corporation
Thompson A. M.
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