Integrated decoupling capacitors

Details Integrated decoupling capacitors Integrated decoupling capacitors

2003-02-26

2004-11-02

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making passive device

Trench capacitor

C438S387000, C257S308000, C257S532000

Reexamination Certificate

active

06812109

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of integrated circuits and, in particular, to a method of fabricating compact decoupling capacitors within integrated circuits.
BACKGROUND OF THE INVENTION
Integrated circuits, particularly those used in computer systems, continuously become more powerful and operate at faster speeds. To supply power to circuit components, metal layers dedicated to power supply distribution are formed in the circuits in order to maintain a low inductive voltage drop. The inductive voltage drop can nevertheless be substantial, causing high frequency noise that is superimposed upon the power supply voltage. For future generations of components with multi-GHz chips, in particular, noise in the power and ground lines increasingly becomes a problem.
Bypass capacitors or decoupling capacitors, which act as a charge reservoir, provide an effective way to suppress the power distribution noise. Additionally, decoupling capacitors provide better electrical performance of the integrated circuit. As a result of these benefits, decoupling capacitors are used in many circuit designs.
Decoupling capacitors have been formed over underlying circuitry and/or device layers. For example, with reference to
FIG. 1
, circuits
10
have been formed having a substrate
2
and device containing layer
4
. Thereafter, a decoupling capacitor is formed by deposing dielectric layers
6
,
8
, and
11
, and conductive layers
7
and
9
, wherein combined layers indicated by numeral
13
form a decoupling capacitor. As illustrated in
FIG. 2
, the capacitor plate(s) can be connected to the underlying components, or a power source, by forming a connective layer
15
which extends between a capacitor plate
9
and an underlying conductive layer
4
. Insulating surfaces
17
are provided to prevent electrical shorts between conductive layers
7
and
9
.
The existing methods for fabricating decoupling capacitors, however, fall short of increasing industry demands that require new performance criteria from supporting components, such as better location within the integrated circuit and higher performance parameters in high-speed environments. What is needed is a method of fabricating decoupling capacitors that are compact, have high-performance characteristics, and are located strategically within the integrated circuit to decouple transient noise and other undesirable signals.
SUMMARY OF THE INVENTION
The present invention discloses a method of fabricating compact decoupling capacitors that are buried in a substrate, and are located strategically to decouple transient noise and other undesirable signals.
A method of forming decoupling capacitors for reducing undesirable noise in an integrated circuit is disclosed, comprising forming an opening within a substrate, where the opening contains fin-like spacers, depositing a dielectric material over the spacers, depositing an electrode material over the dielectric material, depositing an insulative material over the electrode material, and forming integrated circuit components over the insulative material.
Additional features and advantages of the present invention will be more clearly apparent from the detailed description which is provided in connection with accompanying drawings which illustrate exemplary embodiments of the invention.


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U.S. patent application Publication No. US 2002/0036336 A1, published on Mar. 28, 2002.

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