Integrated DDR/SDR flow control managers that support...

Details Integrated DDR/SDR flow control managers that support... Integrated DDR/SDR flow control managers that support...

2006-07-25

2006-07-25

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Serial read/write

C365S191000, C365S233100

Reexamination Certificate

active

07082071

ABSTRACT:
An integrated circuit chip includes a plurality of independent FIFO memory devices that are each configured to support all four combinations of DDR and SDR write modes and DDR and SDR read modes and collectively configured to support all four multiplexer, demultiplexer, broadcast and multi-Q operating modes.

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Invitation to Pay Additional Fees, Annex to Form PCT/ISA/206, Communication Relating to the Results of the Partial International Search, PCT/US02/26516, Oct. 13, 2003.

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