Integrated CPU and memory controller utilizing a communication l

Details Integrated CPU and memory controller utilizing a communication l Integrated CPU and memory controller utilizing a communication l

1998-06-17

2000-11-14

Etienne, Ario

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710129, 710107, 710 61, G06F 1338

Patent

active

061483575

ABSTRACT:
An integrated circuit includes a central processing unit, a memory controller circuit for interfacing to system memory, and an interconnect bus controller for interfacing to an interconnect bus. The interconnect bus controller gives priority to transfer of asynchronous data during a first transfer mode and priority to transfer of isochronous data during a second transfer mode. A switch selectively couples the CPU, the memory controller circuit and the interconnect bus controller.

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