Integrated CMOS circuit comprising a substrate bias voltage gene

Details Integrated CMOS circuit comprising a substrate bias voltage gene Integrated CMOS circuit comprising a substrate bias voltage gene

1987-09-08

1989-04-11

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307592, H03K 1716, H03K 1714, H03K 1706, H01L 2702

Patent

active

048209368

ABSTRACT:
In CMOS integrated circuits, "latch-up" problems may arise if no special steps are taken. One way to counteract a "latch-up" state is to apply a substrate bias voltage. In an integrated circuit, an externally-clocked substrate bias voltage pump and a stand-by bias voltage generator are provided, the latter not being switched on until the substrate bias voltage becomes less negative than, for example, -2V. As a result, the integrated circuit becomes less sensitive to "latch-up", especially during measuring and testing procedures, in which no external clock signal is supplied.

REFERENCES:
patent: 4377756 (1983-03-01), Yoshihara et al.
patent: 4378506 (1983-03-01), Taira
patent: 4439692 (1984-03-01), Beekmans et al.
patent: 4503339 (1985-03-01), Tsuge et al.
Cassidy et al., "Substrate Voltage Regulator", IBM Tech. Discl. Bull., vol. 27, No. 2, pp. 1137-1138, Jul. 1984.

Affiliated with

Also associated with

Rating

Integrated CMOS circuit comprising a substrate bias voltage gene does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated CMOS circuit comprising a substrate bias voltage gene, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated CMOS circuit comprising a substrate bias voltage gene will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-668938