Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
1999-11-09
2001-05-29
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S277000, C327S283000
Reexamination Certificate
active
06239642
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application claims the benefit of Korean Patent Application No. 98-48168, filed Nov. 11, 1998 and Korean Patent Application No. 99-15892, filed May 3, 1999, the disclosure of each of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates to integrated circuits and methods of operating thereof, and more particularly, to signal transmission circuits and methods for controlling signal transmission.
BACKGROUND OF THE INVENTION
Integrated circuits typically include circuit such as delay locked loops (DLLs) that provide distributed signals, e.g., clock signals, to multiple circuits. A DLL typically receives a reference clock signal from which it generates an internal clock signal, the phase of which typically depends on the reference clock signal. It may be desirable to operate a large number of circuits in synchronism with such an internal clock signal. If these circuits are driven in common, the total output load on the DLL can be very large, causing the DLL to consume a large amount of power. Consequently, integrated circuits such as merged memory logic (MML) devices, Rambus dynamic random access memories (RDRAMs), and double data rate (DDR) DRAMs often generate a plurality of synchronized DLL outputs (phases) and utilize a plurality of operation modes, such that the output signals produced by a circuit such as a DLL are selectively applied to circuits in the device to reduce unnecessary power consumption.
Proper operation of a device including a circuit such as a DLL often requires that phases produced by the circuit are accurately synchronized. However, because these output may be differently loaded, such synchronization may be problematic. Consequently, conventional DLLs may include delay circuits that can introduce delay into signals produced by the DLL.
FIG. 1
is a diagram of such a delay circuit, and
FIG. 2
is a waveform diagram illustrating operations for such a circuit. When an input signal S
1
to a first inverter G
1
changes from a logic low level to a logic high level, a signal line n
1
is driven low. However, because of charge stored in a capacitor C, the voltage at the signal line n
1
falls more slowly than the corresponding rise in the input signal S
1
. This introduces a delay in the signal S
2
generated by second inverter G
2
connected to the signal line n
1
with respect to the input signal S
1
. This delay can be reduced by opening the fuse F. However, the delay control afforded by the fuse F may be somewhat limited.
SUMMARY OF THE INVENTION
In light of the foregoing, it is an object of the present invention to provide improved control of transmission time for signals on a signal line of an integrated circuit.
This an other objects features and advantages may be provided according to the present invention by variable loading circuits and methods of operation thereof in which a loading control circuit variably couples a signal line of an integrated circuit to a signal node (e.g., a power supply node or a signal ground node) via a capacitor, responsive to a control signal applied to the loading control circuit. The variable loading circuit may further include a control signal generating circuit that generates the control signal. The loading control circuit may include a series combination of a fuse and one or more switches, e.g., MOS transistors, that are responsive to the control signal. The capacitor may be coupled to a control signal line generated by the control signal generating circuit. The fuse and switches of the various embodiments may be programmed and controlled, respectively, to provide flexible control of signal transmission time.
In particularly, according to an aspect off the present invention, a variable loading circuit for controlling signal transmission on a signal line in an integrated circuit includes a capacitor. A loading control circuit is responsive to a control signal to variably couple the signal line and a signal node through the capacitor and thereby vary signal transmission time on the signal line.
In embodiments of the present invention, the loading control circuit includes a series combination of a fuse and one or more switches. The one or more switches are responsive to respective control signals to variably couple the signal line to the signal node through the fuse and the capacitor. The one or more switches and the capacitor may include respective MOS transistors. The signal node may be a power supply node or a signal ground. The variable loading circuit may further include a control signal generating circuit coupled to the one or more switches and operative to generate one or more control signals for the one or more switches.
According to another aspect of the present invention, a variable signal transmission circuit includes an input circuit, such as a buffer, inverter or logic gate, configured to receive an input signal and to produce an intermediate output signal on an intermediate signal line. An output circuit, such as another buffer, inverter or logic gate, is configured to receive the intermediate output signal and to produce an output signal therefrom. A variable loading circuit includes a capacitor and a loading control circuit responsive to a control signal to variably couple the intermediate signal line and a signal node through the capacitor. The loading control circuit may include a series combination of a fuse and one or more switches, wherein the one or more switches are responsive to respective control signals to variably couple the intermediate signal line to the signal node through the fuse and the capacitor.
According to method aspects of the present invention, signal transmission on a signal line is controlled by generating a control signal and coupling the signal line and a signal node through a capacitor responsive to the control signal to thereby vary signal transmission time on the signal line. A signal transmission time or a capacitance for the signal line may be determined. The control signal may be generated based on the determined signal transmission time or capacitance. By varying transmission time (or capacitance) on multiple signal lines, signal skew between signals can be controlled.
REFERENCES:
patent: 4716302 (1987-12-01), Flannagan et al.
patent: 4894791 (1990-01-01), Jiang et al.
patent: 5428310 (1995-06-01), Casper et al.
patent: 5896059 (1999-04-01), Durham et al.
patent: 5936474 (1999-08-01), Rousselin
patent: 61-255600 (1986-11-01), None
Hwang Sung-min
Kim Jong-Sun
Song Ho-sung
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
Tran Toan
LandOfFree
Integrated circuits with variable signal line loading... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuits with variable signal line loading..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuits with variable signal line loading... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2570589