Integrated circuits with scalable design

Details Integrated circuits with scalable design Integrated circuits with scalable design

2001-12-03

2004-07-06

Garbowshi, Leigh M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06760900

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The invention relates generally to analog or hybrid integrated circuits. The invention more particularly relates to design methodologies that facilitate migrating designs for such circuits to different feature size technologies.
BACKGROUND
Lithography, such as electron beam lithography, is well known in the MOS (metal oxide semiconductor) arts. Progressively higher component densities have been achieved over time by printing progressively smaller features upon semiconductor wafers. This trend of scaling down is expected to continue for some time. Generally, the width of the smallest allowable feature, such as a conductive track, is quoted to specify a particular scaling and a set of design rules corresponding thereto is created. Or, equivalently the Lambda may be cited. The use of the Lambda parameter is well known in the semiconductor manufacturing arts. Thus, CMOS (complementary MOS) design rules for printing features as small as 0.35 microns (micrometer) are referred to as “0.35 micron design rules”. Over time, design rules have evolved from 0.35 micron to 0.25, 0.18, 0.13, 0.08 micron and beyond. Also, over time, there is a trend to use lower powers and operating voltages. Design rules may specify many things, for example, upper and lower bounds for feature dimensions and for voltages. In particular, they specify, amongst other things, the minimum required size of and spacing between particular features, depending upon the power supply and signal voltages to be used.
MOS processes and corresponding design rules have primarily been used for creating digital micro-circuits. Automated design systems for schematic capture, layout and mask generation for digital chips are available and incorporate design rules appropriate to the targeted manufacturing process. Typically, in digital chips, only those transistors that interface to external (off-chip) circuits experience glitches or other large voltage excursions. The transistors that interface off-chip are designated IO transistors (input-output transistors). Such designation, within an automated design system, permits an automated layout generator to follow design rules for features that will withstand the wider voltage specifications necessary (or merely desirable) in dealing with circuit features that conduct off-chip.
MOS processes are also used for analog designs including hybrid micro-circuit designs. Hybrid micro-circuit designs are mixed inter-operating digital and analog circuits sharing a single die. A typical hybrid design is a RF (radio frequency) transceiver circuit incorporating digital signal processing. In MOS analog designs there are design problems not ordinarily found in digital designs and consequently analog designs may not generally be considered to be scalable, i.e., manual conversion and layout of some circuit features are required when migrating to a smaller feature technology. This occurs for multiple reasons. Intentional operation in a triode region and corresponding biasing requirements may be one such reason. Another is that in analog microcircuits, transistors that are not IO transistors may be subject to large voltage excursions, for example, due to insufficient isolation from an IO transistor or due to standing wave collision.
Thus, a need exists to improve the scalability of analog and hybrid MOS design methods, and for MOS chips with reduced overall product cycle costs pursuant to such methods.
SUMMARY OF THE INVENTION
According to a first aspect of the invention, a method for designing IC masks is disclosed. The method may involve generating a schematic, entering transistor data into a CAD system, identifying the I/O transistors and/or the high voltage transistors, designating robust geometries for, and generating the masks.
According to a further aspect of the invention, an integrated circuit comprising a metal oxide semiconductor die formed by lithography using at least one mask is disclosed. The at least one mask may be designed by methods according to the first aspect of the invention.


REFERENCES:
patent: 5598344 (1997-01-01), Dangelo et al.
patent: 5754826 (1998-05-01), Gamal et al.
Baghai et al., “Challanges in CMOS Mixed-Signal Designs for Analog Circuit Designers,” 1997 Proceedings 40th Midwest Symposium on Circuits & Systems, pp. 47-50.*
Berkcan et al., “Physical Assembly for Analog Compilation of High Voltage ICs,” IEEE 1988 Custom ICs Conference, pp. 14.3.1-14.3.7.

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