Integrated circuits with reduced substrate capacitance

Details Integrated circuits with reduced substrate capacitance Integrated circuits with reduced substrate capacitance

2000-10-31

2003-05-13

Coleman, William David (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S450000

Reexamination Certificate

active

06562666

ABSTRACT:

FIELD OF THE INVENTION
The field of the invention is SOI (Silicon On Insulator) CMOS circuits employing wafers formed using any one of possible methods, such as SIMOX, bond and etchback, SMARTCUT, etc.
BACKGROUND OF THE INVENTION
In the field of SIMOX SOI wafer manufacture, it is known that the implantation process to produce industry standard wafers having an insulating layer about 0.4 &mgr;m thick is time consuming and causes defects in the silicon device layer. The art has experimented with reducing both the magnitude of the oxygen implant dose and the thickness of the implanted layer.
A significant drawback of the use of a lower thickness buried oxide (BOX) is that the capacitance from the sources and drains of the transistors to the substrate below the BOX increases as the thickness is reduced. That capacitance increase is reflected in a reduction of circuit performance. The same capacitance increase will also apply to other components such as diodes, resistors, and inductors.
U.S. Pat. No. 5,994,759 teaches the formation of a doped layer under the BOX, creating an n-type layer in a p-type substrate, and then biasing this layer to form a thick depleted layer. In that approach, however, the n-type layer creates a ground plane underneath the BOX. The capacitance from the sources and drains and other circuit elements to the ground plane will be the same as, or greater than the capacitance to the original substrate.
The art has sought a thinner BOX layer having the capacitance of the thicker BOX without success.
SUMMARY OF THE INVENTION
The invention relates to a method of decreasing capacitance between circuit elements in SOI CMOS circuits and the p-doped substrate below the buried oxide (BOX) layer by implanting a lightly doped electrically unbiased area of n-type dopant at the bottom of the BOX, preferably thereby forming a fully-depleted region.


REFERENCES:
patent: 5185535 (1993-02-01), Farb et al.
patent: 5294821 (1994-03-01), Iwamatsu
patent: 5426062 (1995-06-01), Hwang
patent: 5523602 (1996-06-01), Horiuchi et al.
patent: 5663588 (1997-09-01), Suzuki et al.
patent: 5760442 (1998-06-01), Shigyo et al.
patent: 5795810 (1998-08-01), Houston
patent: 5810994 (1998-09-01), Lee et al.
patent: 5923067 (1999-07-01), Voldman
patent: 5939755 (1999-08-01), Takeuchi et al.
patent: 5955767 (1999-09-01), Liu et al.
patent: 5989981 (1999-11-01), Nakashima et al.
patent: 5994759 (1999-11-01), Darmawan et al.
patent: 6100567 (2000-08-01), Burr
Sze, “Semiconductor Devices Physics and Technology”, John Wiley & Sons, New York, 1985, pp 74-82.

Affiliated with

Also associated with

Rating

Integrated circuits with reduced substrate capacitance does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated circuits with reduced substrate capacitance, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuits with reduced substrate capacitance will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3086221