Integrated circuits with parallel self-testing

Details Integrated circuits with parallel self-testing Integrated circuits with parallel self-testing

2005-02-08

2005-02-08

Le, Thong Q. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S222000

Reexamination Certificate

active

06853597

ABSTRACT:
An integrated circuit having a BIST control unit for testing a plurality of memory banks simultaneously is described. The BIST control unit is coupled to a plurality of comparator units. In one embodiment, a comparator unit is coupled to a memory bank to facilitate parallel testing.

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