Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
1999-05-13
2001-05-22
Nelms, David (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S040000, C326S041000
Reexamination Certificate
active
06236229
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit devices as well as to methods for personalizing and programming such devices and resulting integrated circuit devices.
BACKGROUND OF THE INVENTION
Various types of personalizable integrated circuits and programmable integrated circuits are known in the art. Personalizable integrated circuits include gate arrays, such as laser programmable gate arrays, commonly known as LPGA devices, which are described, inter alia in the following U.S. Pat. Nos. 4,924,287; 4,960,729; 4,933,738; 5,111,273; 5,260,597; 5,329,152; 5,565,758; 5,619,062; 5,679,967; 5,684,412; 5,751,165; 5,818,728. Devices of this type are personalized by etching or laser ablation of metal portions thereof.
There are also known field programmable gate arrays, commonly known as FPGA devices, programmable logic devices, commonly known as PLD devices as well as complex programmable logic devices, commonly known as CPLD devices. Devices of these type are programmable by application of electrical signals thereto.
Programmable logic devices are known in which programmable look up tables are employed to perform relatively elementary logic functions. Examples of such devices appear in U.S. Pat. Nos. 3,473,160 and 4,706,216. Multiplexers are also known to be used as programmable logic elements. Examples of such devices appear in U.S. Pat. Nos. 4,910,417, 5,341,041 and 5,781,033. U.S. Pat. Nos. 5,684,412, 5,751,165 and 5,861,641 show the use of multiplexers to perform customizable logic functions.
Problems of clock skew in gate arrays are well known. U.S. Pat. No. 5,420,544 describes a technique for reducing clock skew in gate arrays which employs a plurality of phase adjusting devices for adjusting the phase at various locations in gate arrays. Various clock tree design structures have been proposed which produce relatively low clock skew.
PCT Published Patent Application WO 98/43353 describes a functional block architecture for a gate array.
U.S. Pat. No. 5,825,202 describes an integrated semiconductor device comprising a FPGA portion connected to a maskdefined application specific logic area.
SUMMARY OF THE INVENTION
The present invention seeks to provide an improved integrated circuit which employs look up tables to provide highly efficient logic cells and logic functionalities.
There is thus provided in accordance with a preferred embodiment of the present invention a logic cell for use in a logic array, the logic cell including:
at least one look-up table including a plurality of LUT inputs and at least one output; and
at least one logic gate having a plurality of logic inputs and an output coupled to one of the plurality of LUT inputs.
According to one embodiment of the invention, the logic gate is a 2-input logic gate. According to an alternative embodiment of the invention, the logic gate is a NAND gate.
Preferably, the at least one look-up table includes at least one pair of look-up tables.
In accordance with a preferred embodiment of the invention, the logic cell also includes a multiplexer receiving outputs from the at least one pair of look-up tables.
In accordance with another preferred embodiment of the invention, the at least one look-up table includes first and second pairs of look-up tables, the logic cell also including first and second multiplexers, each multiplexer receiving outputs from a pair of look-up tables.
Preferably, the logic cell also includes a third multiplexer receiving outputs from the first and second multiplexers.
Additionally in accordance with a preferred embodiment of the present invention, the logic cell also includes a flip-flop for receiving an output from the first multiplexer.
In accordance with an alternative embodiment of the present invention, the logic cell also includes a multiplexer connected to an output of at least one look-up table and an inverter selectably connectable to at least one of an output of the multiplexer and an output of the look-up table.
The look-up table is preferably a programmable look-up table.
In accordance with a preferred embodiment of the present invention, the logic cell also includes a metal interconnection layer overlying at least a portion of the cell for providing a custom interconnection between components thereof.
There is also provided in accordance with a preferred embodiment of the present invention a semiconductor device including a logic array including a multiplicity of identical logic cells, each identical logic cell including at least one look-up table, a metal connection layer overlying the multiplicity of identical logic cells for providing a permanent customized interconnect between various inputs and outputs thereof.
Preferably each device includes at least one multiplexer and the at least one look-up table provides an input to the at least one multiplexer.
Additionally, each device preferably also includes at least one logic gate connected to at least one input of the look-up table.
According to one embodiment of the invention, the logic gate is a 2-input logic gate. According to an alternative embodiment of the invention, the logic gate is a NAND gate connected to an input of the at least one look-up table.
Preferably, the at least one look-up table includes at least one pair of look-up tables.
In accordance with a preferred embodiment of the present invention, the at least one multiplexer receives outputs from the at least one pair of look-up tables. Preferably, the at least one multiplexer is configured to perform a logic operation on the outputs from the at least one pair of look-up tables.
In accordance with an embodiment of the invention, the at least one look-up table includes first and second pairs of look-up tables and the at least one multiplexer includes first and second multiplexers, each multiplexer receiving outputs from a pair of look-up tables.
Preferably, the look-up table is programmable.
In accordance with a preferred embodiment of the present invention, the device includes at least one simple logic gate selectably connected to at least one logic cell output.
Preferably, the simple logic gate is a two-input logic gate. Alternatively it may be an inverter or a buffer.
The device preferably also includes a multiplexer connected to an output of at least one look-up table and an inverter selectably connectable to an output of the at least one multiplexer.
In accordance with a preferred embodiment of the present invention, the device also includes a metal interconnection layer overlying at least a portion of the cell for providing a custom interconnection between components thereof.
There is also provided in accordance with a preferred embodiment of the present invention a logic array including at least one logic cell, the logic cell including:
at least one look-up table including a plurality of LUT inputs and at least one output; and
at least one logic gate having a plurality of logic inputs and an output coupled to one of the plurality of LUT inputs.
The at least one look-up table is preferably a programmable look-up table.
According to one embodiment of the invention, the logic array is a 2-input logic gate. According to an alternative embodiment of the invention, the logic gate is a NAND gate.
Preferably, the at least one look-up table includes at least one pair of look-up tables.
In accordance with a preferred embodiment of the invention, the logic array also includes a multiplexer receiving outputs from the at least one pair of look-up tables.
In accordance with another preferred embodiment of the invention, the at least one look-up table includes first and second pairs of look-up tables, the logic cell also including first and second multiplexers, each multiplexer receiving outputs from a pair of look-up tables.
Preferably, the logic array also includes a third multiplexer receiving outputs from the first and second multiplexers.
Additionally in. accordance with a preferred embodiment of the present invention, the logic array also includes a flip-flop for receiving an output from the first multiplexer.
In accordance with an alternative
eASIC Corporation
Gluck Jeffrey W.
Le Thong
Nelms David
Venable
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