Active solid-state devices (e.g. – transistors – solid-state diode – Responsive to non-electrical signal – Electromagnetic or particle radiation
Reexamination Certificate
2006-02-07
2006-02-07
Wille, Douglas (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Responsive to non-electrical signal
Electromagnetic or particle radiation
C385S014000
Reexamination Certificate
active
06995441
ABSTRACT:
An integrated circuit with a number of optical waveguides that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor wafer. The optical waveguides include a highly reflective material that is deposited so as to line an inner surface of the high aspect ratio holes which may be filled with air or a material with an index of refraction that is greater than 1. These metal confined waveguides are used to transmit signals between functional circuits on the semiconductor wafer and functional circuits on the back of the wafer or beneath the wafer.
REFERENCES:
patent: 3968564 (1976-07-01), Springthorpe
patent: 4920070 (1990-04-01), Mukai
patent: 4970578 (1990-11-01), Tong et al.
patent: 5128831 (1992-07-01), Fox, III et al.
patent: 5200631 (1993-04-01), Austin et al.
patent: 5221633 (1993-06-01), Holm et al.
patent: 5352998 (1994-10-01), Tamino
patent: 5362976 (1994-11-01), Suzuki
patent: 5409563 (1995-04-01), Cathey
patent: 5416872 (1995-05-01), Sizer, II et al.
patent: 5431775 (1995-07-01), Prince
patent: 5489554 (1996-02-01), Gates
patent: 5532506 (1996-07-01), Tserng
patent: 5587119 (1996-12-01), White
patent: 5604835 (1997-02-01), Nakamura et al.
patent: 5641545 (1997-06-01), Sandhu
patent: 5652811 (1997-07-01), Cook et al.
patent: 5656548 (1997-08-01), Zavracky et al.
patent: 5682062 (1997-10-01), Gaul
patent: 5729038 (1998-03-01), Young et al.
patent: 5742100 (1998-04-01), Schroeder et al.
patent: 5760478 (1998-06-01), Rozso et al.
patent: 5767001 (1998-06-01), Bertagnolli et al.
patent: 5798297 (1998-08-01), Winnerl et al.
patent: 5834849 (1998-11-01), Lane
patent: 5844289 (1998-12-01), Teranishi et al.
patent: 5848214 (1998-12-01), Haas et al.
patent: 5858814 (1999-01-01), Goossen et al.
patent: 5858877 (1999-01-01), Dennison et al.
patent: 5897333 (1999-04-01), Goossen et al.
patent: 5900674 (1999-05-01), Wojnarowski et al.
patent: 5901050 (1999-05-01), Imai
patent: 5902118 (1999-05-01), Hubner
patent: 5903045 (1999-05-01), Bertin et al.
patent: 6915167 (1999-06-01), Leedy
patent: 5952665 (1999-09-01), Bhargava
patent: 5963088 (1999-10-01), Czamul et al.
patent: 6090636 (2000-07-01), Geusic et al.
patent: 6143616 (2000-11-01), Geusic et al.
patent: 6150188 (2000-11-01), Geusic et al.
patent: 6181864 (2001-01-01), Jang et al.
patent: 6187677 (2001-02-01), Ahn
patent: 6198168 (2001-03-01), Geusic et al.
patent: 6281042 (2001-08-01), Ahn et al.
patent: 6122187 (2001-09-01), Ahn et al.
patent: 56-055067 (1981-05-01), None
patent: 03-013907 (1991-01-01), None
patent: 04-263462 (1992-09-01), None
patent: 05-145060 (1993-06-01), None
patent: WO-91/11833 (1991-08-01), None
patent: WO-94/05039 (1994-03-01), None
Forbes, L., et al., “Resonant Forward-Biased Guard-Ring Diodes for Suppression of Substrate Noise in Mixed-Mode CMOS Circiuts”,Electronics Letters,31, (Apr. 1995), 720-721.
Foster, R., et al., “High Rate Low-Temperature Selective Tungsten”,In: Tungsten and Other Refractory Metals for VLSI Applications III,V.A. Wells, ed., Materials Res. Soc., Pittsburgh, PA. (1988),69-72.
Gong, S., et al., “Techniques for Reducing Switching Noise in High Speed Digital Systems”,Proceedings of the 8th Annual IEEE International ASICConference and Exhibit, Austin, TX,(1995),21-24.
Heavens, O.,Optical Properites of Thin Solid Films,Dover Pubs. Inc., New York, (1965), 155-206.
Horie, H., et al., et al., “Novel High Aspect Ratio Aluminum Plug for Logic/DRAM LSI's Using Polysilicon-Aluminum Substitute”,Technical Digest: IEEE International Electron Devices Meeting, San Francisco, CA,(1996),946-948.
Kim, Y.S., et al., “Study on Pyrolysis DMEAA for Selective Deposition of Aluminum”,In Advanced Metallization and Interconnect Systems for ULSI Applications in 1995,R.C. Ellwanger, et al., (eds.), Materials Research Society, Pittsburgh, PA,(1996),675-680.
Klaus, et al., “Atomic Layer Controlled Growth of SiO2 Films Using Binary Reactions Sequence Chemistry”,Applied Physics Lett. 70(9),(Mar. 3, 1997), 1092-94.
Lehmann, et al., “A Novel Capacitor Technology Based on Porous Silicon”,Thin Solid Films 276, Elsevier Science,(1996),138-42.
Lehmann, V., “The Physics of Macropore Formation in Low Doped n-Type Silicon”,Journal of the Electrochemical Society,140(10), (Oct. 1993),2836-2843.
Masu, K., et al., “Multilevel Metallization Based on A1 CVD”,1996 IEEE Symposium on VLSI Technology, Digest of Technical Papers,Honolulu, HI, (Jun. 11-13, 1996),44-45.
McCredie, B.D., et al., “Modeling, Measurement, and Simulation of Simultaneous Switching Noise”,IEEE Transactions on Components, Packaging, and Manufacturing Technology —Part B, 19,(Aug. 1996),461-472.
Muller, K., “Trench Storage Node Technology for Gigabit DRAM Generations”,Digest IEEE International Electron Devices Meeting,San Francisco, CA,(Dec. 1996),507-510.
Ohba, T., et al., “Evaluation on Selective Deposition of CVD W Films by Measurement of Surface Temperature”,In; Tungstn and Other Refractory Metals for VSLI Applications II,Materials Research Society, Pittsburgh, PA.(1987),59-66.
Ohba, T., et al., “Selective Chemical Vapor Deposition of Tungsten Using Silane and Polysilane Reductions”,In: Tungsten and Other Refractory Metals for VLSI Applications IV,Materials Research Society, Pittsburgh, PA, (1989),17-25.
OTT, A W. et al., “AI303 Thin Film Growth on Si(100) Using Binary Reaction Sequence Chemistry”,Thin Solid Films,vol. 292, (1997),135-44.
Ramo, S., et al.,Fields and Waves in Communication Electronics, Third Edition,John Wiley & Sons, Inc., (1994),pp. 428-433.
Senthinathan, R., et al., “Reference Plane Parasitics Modeling and Their Contribution to the Power and Ground Path “Effective” Inductance as Seen by the Output Drivers”,IEEE Transactions on Microwave Theory and Techniques,42, (Sep. 1994),1765-1773.
Stanisic, B. R., et al., “Adressing Noise Decoupling in Mixed-Signal IC's: Power Distribution Design and Cell Customization”,IEEE Journal of Solid-State Circuits 30,(Mar. 1995),321-326.
Su, D. K., et al., “Experimental Results and Modeling Techniques for Substrate Noise in Mixed Signal Integrated Circuits”,IEEE Journal of Solid State Circuits,vol. SC-28, (1993),420-30.
Suntola, Y., “Atomic Layer Epitaxy”,Handbook of Crystal Growth, 3: Thin Films of Epitaxy, Part B: Growth Mechanics and Dynamics,Amsterdam,(1994),pp. 601-683.
Vittal, A. et al., “Clock Skew Optimization for Ground Bounce Control”,1996 IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers,San Jose, CA,(Nov. 10-14, 1996),395-399.
Sze, S.M.,VLSI Technology, 2nd Edition, Mc Graw-Hill, NY,(1988),90.
Ahn Kie Y.
Forbes Leonard
Geusic Joseph E.
Schwegman, Lunberg, Woessner & Kluth, P.A.
Wille Douglas
LandOfFree
Integrated circuits using optical waveguide interconnects... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuits using optical waveguide interconnects..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuits using optical waveguide interconnects... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3691159