Integrated circuits that include a barrier layer reducing hydrog

Details Integrated circuits that include a barrier layer reducing hydrog Integrated circuits that include a barrier layer reducing hydrog

1997-03-17

1998-10-20

Tran, Minh-Loan

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257537, 257538, 257646, 257751, 257754, H01L 2976, H01L 2358

Patent

active

058250689

ABSTRACT:
A barrier layer impedes hydrogen diffusion into polysilicon resistors in circuits in which the resistor resistivity is sensitive to hydrogen diffusion into the resistors. The barrier layer extends laterally throughout the whole integrated circuit except for contact areas in which circuit elements overlying the barrier layer contact conductive elements underlying the barrier layer. The barrier layer includes a layer of polysilicon or amorphous silicon. In some embodiments, the barrier layer includes multiple layers of polysilicon or amorphous silicon that are separated by thin layers of silicon dioxide. In some embodiments, the barrier layer is formed between the polysilicon resistor and PECVD silicon nitride passivation which contains atomic hydrogen.

REFERENCES:
patent: 4319953 (1982-03-01), Grabmaier
patent: 4923562 (1990-05-01), Jucha et al.
patent: 5057897 (1991-10-01), Nariani et al.
patent: 5128279 (1992-07-01), Nariani et al.
patent: 5164338 (1992-11-01), Graeger et al.
patent: 5290727 (1994-03-01), Jain et al.
patent: 5336335 (1994-08-01), Hall et al.
patent: 5349325 (1994-09-01), McAllister
patent: 5374833 (1994-12-01), Nariani et al.
patent: 5382549 (1995-01-01), Ohshima et al.
patent: 5393687 (1995-02-01), Liang
patent: 5457335 (1995-10-01), Kuroda et al.
patent: 5492865 (1996-02-01), Nariani et al.
Hoshi, N., et al., "1.0 u.mu. CMOS Process for Highly Stable Tera-Ohm Polysilicon Load 1Mb SRAM", IEEE, International Electron Devices Meeting, Dec. 7-10, 1986 (Los Angeles), pp. 300-303.
Yoshida, S., et al., "Improvement of Endurance to Hot Carrier Degradation by Hydrogen Blocking P-Sio", IEEE, International Electron Devices Meeting, Dec. 11-14, 1988 (San Francisco), pp. 22-25.
Karp., J.A., et al., "A 4096-Bit Dynamic MOS RAM", 1972 ISSCC Digest, pp. 144-145 (includes attachments from IEEE International Solid-State Circuits Conference, Feb. 19, 1969); (Pennsylvania), pp. 36-47.
Kamins, T., "Polycrystalline Silicon For Integrated Circuit Applications" (Kluwer Academic Publishers, Norwell, MA, 1988), pp. 159, 186-189, 212-215.
Wolf, S., et al., "Silicon Processing for the VLSI Era: vol. I--Process Technology" (Lattice Press, Sunset Beach, CA, 1986), pp. 177-181, 184, 191-194.
Wolf, S., "Silicon Processing for the VLSI Era: vol. II--Process Integration" (Lattice Press, Sunset Beach, CA, 1990), pp. 245-251.
Wolf, S., "Silicon Processing for the VLSI Era: vol. III--The Submicron MOSFET" (Lattice Press, Sunset Beach, CA, 1995), pp. 559-661.

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