Integrated circuits having reduced timing skew among signals...

Details Integrated circuits having reduced timing skew among signals... Integrated circuits having reduced timing skew among signals...

1999-05-18

2002-04-09

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230030, C365S051000, C365S063000

Reexamination Certificate

active

06370079

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of integrated circuits in general and more particularly to the arrangement of components in integrated circuits.
BACKGROUND OF THE INVENTION
Timing skew may be introduced between signals transmitted in an integrated circuit because some of the signals may propagate greater or lesser distances than others. For example, if two data signals in an integrated circuit memory propagate via different paths to output pads on the integrated circuit memory, the data signals may arrive at the data pads at different times. Unfortunately, as the layout of the integrated circuit occupies more area of a chip, the data signals may need to propagate greater distances. For example, as the capacity of an integrated circuit memory increases, more memory cell arrays may be included. Consequently, the difference in propagation times for data signals from different memory cell arrays may be increased as the number of memory cell arrays increases.
FIG. 1
is a block diagram that illustrates a conventional arrangement of an integrated circuit. Memory cell arrays
10
-
1
through
10
-
16
are organized in a left bank that includes the memory cell arrays
10
-
1
through
10
-
8
and a right bank that includes the memory cell arrays
10
-
9
through
10
-
16
which are separated by a column address decoder
16
located in a central region therebetween. Input/output line (IOL) pairs IOL
0
/B
0
through IOL
7
/B
7
are located between the memory cell arrays in the left bank and the input/output line pairs IOL
8
/B
8
through IOL
16
/B
16
are located between the memory cell arrays in the right bank. The IOL pair located between the respective memory cell arrays are shared by the adjacent memory cell arrays. For example, IOL pair IOL
2
/B
2
and IOL
3
/B
3
located between the memory cell arrays
10
-
1
,
10
-
2
are shared to provided data to and from memory cell arrays
10
-
1
,
10
-
2
.
Data line pairs DIOL
0
/B
0
through DIOL
3
/B
3
are horizontally arranged above the left bank of memory cell arrays
10
-
1
through
10
-
8
. Data line pairs DIOL
4
/B
4
through DIOL
7
/B
7
are horizontally arranged above DIOL
0
/B
0
through DIOL
3
/B
3
. Data input/output line pairs DIOL
8
/B
8
through DIOL
11
/B
11
are horizontally arranged above the right bank of memory cell arrays
10
-
9
through
10
-
16
. Data line pairs DIOL
12
/B
12
through DIOL
15
/B
15
are horizontally arranged above the data input/output line pairs DIOL
8
/B
8
through DIOL
11
/B
11
.
Data input/output selection circuits
12
-
1
through
12
-
9
are horizontally arranged between the memory cell arrays
10
-
1
through
10
-
8
and the data input/output line pairs DIOL
0
/B
0
through DIOL
3
/B
3
. Data input/output selection circuits
12
-
10
through
12
-
18
are arranged between the memory cell arrays
10
-
9
through
10
-
18
and the data input/output line pairs DIOL
8
/B
8
through DIOL
11
/B
11
. Input/output sense amplifiers
14
-
1
,
14
-
3
are respectively connected to the data input/output line pairs DIOL
0
/B
0
through DIOL
3
/B
3
and data input/output line pairs DIOL
8
/B
8
through DIOL
11
/B
11
. Input/output sense amplifiers
14
-
2
,
14
-
4
are located above the column address decoder
16
and are respectively connected to data input/output line pairs DIOL
4
/B
4
through DIOL
7
/B
7
and DIOL
12
/B
12
through DIOL
15
/B
15
.
Data input/output pads DQ
0
, DQ
1
, DQ
2
, DQ
3
, DQ
8
, DQ
9
, DQ
10
, D
11
are horizontally and linearly arranged on the right top side of the memory, and data input/output pads DQ
4
, DQ
5
, DQ
6
, DQ
7
, DQ
12
, DQ
13
, DQ
14
, DQ
15
are horizontally and linearly arranged on the right bottom side of the memory as shown in FIG.
1
.
During a write operation, the memory cell arrays
10
-
1
through
10
-
16
transfer data from the input/output line pairs to bit line pairs (not shown) in response to block control signals C
0
, C
1
, C
2
and C
3
. During a read operation, the memory cell arrays
10
-
1
through
10
-
16
transfer data from the bit line pairs to the input/output line pairs. Generally, the block control signals C
0
through C
3
may be generated by using a row address signal. The column address decoder
16
decodes a column address to generate column address selection signals Y
0
through Yn. The data input/output selection circuits control transmission of data between the data input/output line pairs and the input/output line pairs. For example, the data input/output selection circuits
12
-
1
,
12
-
2
transmit data from the data input/output line pairs DIOL
0
/B
0
, DIOL
1
/B
1
, DIOL
2
/B
2
, DIOL
3
/B
3
to the input/output line pairs IOL
0
/B
0
, IOL
1
/B
1
, IOL
2
/B
2
, IOL
3
/B
3
during a write operation. The data input/output selection circuits
12
-
1
,
12
-
2
transmit data from the input/output line pairs IOL
0
/B
0
, IOL
1
/B
1
, IOL
2
/B
2
, IOL
3
/B
3
to the data input/output line pairs DIOL
0
/B
0
, DIOL
1
/B
1
, DIOL
2
/B
2
and DIOL
3
/B
3
during a read operation.
Signals that enable the data input/output selection circuits
12
-
1
through
12
-
18
are generated so that the pair of input/output selection circuits adjacent to the selected memory cell arrays are enabled. For example, the data input/output selection circuits
12
-
5
,
12
-
14
are respectively positioned between the memory cell arrays
10
-
4
,
10
-
5
and the data input/output line pairs DIOL
0
/B
0
through DIOL
3
/B
3
, and between the memory cell arrays
10
-
12
,
10
-
13
and the data input/output line pairs DIOL
8
/B
8
through DIOL
11
/B
11
, thereby enabling the input/output line pairs IOL
0
/B
0
, IOL
1
/B
1
to be connected to the respective data input/output line pairs DIOL
0
/B
0
, DIOL
1
/B
1
when the memory cell array block
10
-
4
is selected, and enabling the input/output line pairs IOL
4
/B
4
, IOL
5
/B
5
to be connected to the data input/output line pairs DIOL
4
/B
4
, DIOL
5
/B
5
, respectively.
The input/output sense amplifier
14
-
1
amplifies data from the data input/output line pairs DIOL
0
/B
0
through DIOL
3
/B
3
and outputs the data onto the data input/output pads DQ
0
, DQ
1
, DQ
2
and DQ
3
, or amplifies data input from the data input/output pads DQ
0
, DQ
1
, DQ
2
and DQ
3
and transmits the data to the data input/output line pairs DIOL
0
/B
0
through DIOL
3
/B
3
. Data input/output buffers (not shown) are connected between the input/output sense amplifiers and the data input/output pads. The other input/output sense amplifiers
14
-
2
,
14
-
3
,
14
-
4
perform in a fashion analogous to the operation of the input/output sense amplifier
14
-
1
described above.
During a read operation, the column address decoder
16
decodes the column address to generate the column selection signals Y
1
through Yn. When the block control signal C
0
is enabled and the memory cell arrays
10
-
1
,
10
-
5
,
10
-
12
and
10
-
16
are selected, data output from the memory cells selected by word line of the memory cell array
10
-
1
and column selection signals are transmitted to the input/output line pairs IOL
0
/B
0
through IOL
3
/B
3
. The data input/output selection circuits
12
-
1
,
12
-
2
transmit data from the input/output line pairs IOL
0
/B
0
through IOL
3
/B
3
to the data input/output line pairs DIOL
0
/B
0
through DIOL
3
/B
3
, respectively. Data output from the memory cells selected by column selection signals and word line of the memory cell array
10
-
4
are transmitted onto the input/output line pairs IOL
4
/B
4
through IOL
7
/B
7
positioned on the left and right sides of the memory cell array
10
-
5
. The data input/output selection circuits
12
-
5
,
12
-
6
transmit data from the input/output line pairs IOL
4
/B
4
through IOL
7
/B
7
to the data input/output line pairs DIOL
4
/B
4
through DIOL
7
/B
7
, respectively.
The memory cell arrays
10
-
12
,
10
-
16
and data input/output selection circuits
12
-
14
,
12
-
18
also transmit the data from the corresponding memory cells to the data input/output line pairs D
108
/B
8
through DIO
15
/B
15
, resp

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