Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2001-12-07
2003-11-04
Nguyen, Cuong Quang (Department: 2811)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S424000
Reexamination Certificate
active
06642125
ABSTRACT:
CLAIM FOR PRIORITY
This application claims priority to Korean Patent Application No. 2000-74915, filed on Dec. 9, 2000, the entire disclosure of which is incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates to integrated circuits and methods of forming integrated circuits in general and, more particularly, to shallow trench isolation structures in integrated circuits and methods of forming shallow trench isolation structures in integrated circuits.
BACKGROUND OF THE INVENTION
With the development of semiconductor manufacturing techniques, progress has been made in increasing the speed and integration of semiconductor devices. Local Oxidation Of Silicon (LOCOS) layers have been used as isolation layers in semiconductor devices. However, LOCOS may promote a bird's beak effect at the edges of the isolation layer thus reducing the size of the adjacent active regions and which may adversely affect current leakage.
Referring to
FIG. 1
, a semiconductor substrate
10
includes as a cell region, a core region and a peripheral region. A blocking pattern (not shown) is formed on the semiconductor substrate
10
to expose an isolation region. The blocking pattern may be a stack of an oxide layer and a silicon nitride layer. The exposed semiconductor substrate
10
is etched to a depth using the blocking pattern as a mask to form trenches t
1
and t
2
. The trench t
1
is formed in the cell region and the trench t
2
is used to define a PMOS transistor region in the core and peripheral regions. The trenches t
1
and t
2
can be formed by dry etching using plasma.
The dry etching may cause silicon lattice defects and damage the inner surfaces of the trenches t
1
and t
2
. Conventionally, to reduce such silicon lattice defects and damage, a side wall oxide layer
12
can be formed by thermally oxidizing the inner surfaces of the trenches t
1
and t
2
. Also, the formation of the side wall oxide layer
12
can remove sharp corners generated in the trenches t
1
and t
2
associated with the bird's beak effect discussed above.
Subsequently, a silicon nitride liner
14
can be formed on the side wall oxide layer
12
. The silicon nitride liner
14
may reduce stress due to a difference between the respective thermal expansion coefficients associated with the semiconductor substrate
10
and a silicon oxide layer in the trenches t
1
and t
2
.
A dielectric material, such as a High Density Plasma (HDP) oxide, is deposited on the semiconductor substrate
10
to completely fill the trenches t
1
and t
2
. Next, a Chemical Mechanical Polishing (CMP) process is performed on the HDP oxide and the blocking pattern to expose a surface of the semiconductor substrate
10
to form an STI layer
16
in the trenches t
1
and t
2
which completes the conventional STI structure.
However, the semiconductor device having the conventional STI structure discussed above may cause the following problems. With reference to
FIGS. 2A and 2B
, high energy or “hot” carriers in a MOS transistor can penetrate through the side wall oxide layer
12
into the STI layer
16
. N-type charged carriers, such as electrons
30
, that penetrate into the STI layer
16
may collect at an interface of the silicon nitride liner
14
and the side wall oxide layer
12
and in the silicon nitride liner
14
as shown in FIG.
2
A. The electrons
30
may be trapped at the interface due the thickness of the side wall oxide layer
12
. When a dense region of the electrons
30
collects at the interface, positive holes
32
can be induced at a boundary of the STI layer
16
opposite the electrons
30
as shown in FIG.
2
A.
As shown in
FIG. 2B
, a conductive path through the semiconductor substrate
10
may not be formed between n-type junction regions
26
a
and
26
b
of an N-channel field effect transistor (N-FET) because the major carriers are electrons
30
. However, the holes
32
at the boundary of the STI layer
16
can provide a current path I that electrically connects a p-type junction region
28
a
(associated with a gate electrode of a Metal Oxide Semiconductor (MOSFET)
24
) and
28
b
associated with an adjacent MOSFET. Although the STI structure is located between the p-type junction regions
28
a
and
28
b
, the leakage current can be increased by the current path I which can cause, for example, increased standby current after burn-in of the integrated circuit.
Furthermore, in cases where a channel region of the P-FET is adjacent to the silicon nitride liner
14
where the electrons
30
are trapped, holes may be induced in the channel region of the P-FET thereby affecting the operation of the P-FET. Also, holes induced when the P-FET is turned on may not be easily removed and, therefore, may remain after the P-FET is turned off. The length of the channel of the P-FET may, therefore, be reduced which may decrease the threshold and breakdown voltages associated with the P-FET.
SUMMARY OF THE INVENTION
Embodiments according to the present invention may provide integrated circuits having Shallow Trench Isolation (STI) structures. Pursuant to these embodiments, an integrated circuit substrate can include first and second adjacent p-type doped regions spaced-apart from one another in the integrated circuit substrate. A trench in the integrated circuit substrate is between the first and second adjacent p-type doped regions. An insulator layer in the trench has a side wall, wherein the side wall is free of a layer thereon that reduces a stress between the integrated circuit substrate and the insulator layer.
In some embodiments according to the present invention, a dielectric material is in the trench directly on the side wall. In some embodiments according to the present invention, the trench is a first trench and the side wall is a first side wall and the insulator layer is a first insulator layer. First and second adjacent n-type doped regions are spaced-apart from one another in the integrated circuit substrate. A second trench is in the integrated circuit substrate between the first and second adjacent n-type doped regions. A second insulator layer in the second trench has a second side wall. A liner layer on the second side wall can reduce a stress between the integrated circuit substrate and the second insulator layer.
In some embodiments according to the present invention, the dielectric material is a first dielectric material and a second dielectric material is in the second trench on the liner layer. In some embodiments according to the present invention, the side wall is free of silicon nitride. In some embodiments according to the present invention, the integrated circuit includes a core region, a peripheral region, and a cell region that is spaced apart from the core and peripheral regions and has a greater density of integrated circuit devices therein than the core and peripheral regions, wherein the first trench is in one of the peripheral and core regions. The second trench is in the cell region.
In some embodiments according to the present invention, the integrated circuit includes a core region, a peripheral region, and a cell region that is spaced apart from the core and peripheral regions and has a greater density of integrated circuit devices therein than the core and peripheral regions. The trench is between the core and peripheral regions and the cell region.
In some embodiments according to the present invention, the integrated circuit includes a core region, a peripheral region, and a cell region that is spaced apart from the core and peripheral regions and has a greater density of integrated circuit devices therein than the core and peripheral regions. The trench is in one of the core and peripheral regions.
Pursuant to method embodiments according to the present invention, first and second adjacent p-type doped regions are formed spaced-apart from one another in an integrated circuit substrate. A trench is formed in the integrated circuit substrate between the first and second adjacent p-type doped regions. An insulator layer is formed in the trench having a
Jin Gyo-young
Oh Yong-chul
Myers Bigel & Sibley & Sajovec
Nguyen Cuong Quang
Samsung Electronics Co,. Ltd.
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