Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2011-03-29
2011-03-29
Smith, Zandra (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S206000, C257S211000, C257S314000, C257S390000, C257SE29309, C257SE21613, C257SE21614, C257SE21409, C257SE21656, C257SE21679, C438S257000
Reexamination Certificate
active
07915667
ABSTRACT:
In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.
REFERENCES:
patent: 6362056 (2002-03-01), Tonti et al.
patent: 7714377 (2010-05-01), Specht et al.
patent: 2004/0206996 (2004-10-01), Lee et al.
patent: 2005/0133916 (2005-06-01), Karnezos
patent: 2006/0102952 (2006-05-01), Lee
patent: 2007/0018201 (2007-01-01), Specht et al.
patent: 2007/0252201 (2007-11-01), Kito et al.
patent: 2008/0067583 (2008-03-01), Kidoh et al.
patent: 2008/0073635 (2008-03-01), Kiyotoshi et al.
patent: 2008/0149913 (2008-06-01), Tanaka et al.
patent: 2008/0173932 (2008-07-01), Kidoh et al.
patent: 2008/0180994 (2008-07-01), Katsumata et al.
patent: 2008/0259687 (2008-10-01), Specht et al.
patent: 2008/0315291 (2008-12-01), Kito et al.
patent: 2009/0230449 (2009-09-01), Sakaguchi et al.
patent: 2009/0267135 (2009-10-01), Tanaka et al.
patent: 2010/0059811 (2010-03-01), Sekine et al.
patent: 2010/0109071 (2010-05-01), Tanaka et al.
patent: 2010/0155818 (2010-06-01), Cho et al.
Lee, Y.K., et al., “Multi-Level Vertical Channel SONOS Nonvolatile Memory on SOI,” IEEE, Symposium on VLSI Technology Digest of Technical Papers, 2002, 2 pages.
Beug Florian
Hofmann Franz
Knoefler Roman
Manger Dirk
Riedel Stephan
Economou John S.
Joy Jeremy J
Qimonda AG
Smith Zandra
LandOfFree
Integrated circuits having a contact region and methods for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuits having a contact region and methods for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuits having a contact region and methods for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2703392