Integrated circuits from wafers having improved flatness

Details Integrated circuits from wafers having improved flatness Integrated circuits from wafers having improved flatness

1988-12-23

1989-10-17

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156651, 156653, 156657, 1566591, 1566611, 156662, H01L 21306, B44C 122, C03C 1500, C03C 2506

Patent

active

048744638

ABSTRACT:
An improvement in silicon wafer flatness is obtained by reducing the time spent in polishing the wafer. After a conventional lapping operation, the wafer is coated with an etch resistant coating, typically silicon nitride. A polishing step removes the nitride coating on the flat surfaces of the wafer, but leaves a nitride coating on the sides of pits that are formed in the lapping operation. The wafer is then etched, typically in KOH, to remove the silicon surface to below the depth of the pits. The undercutting of the nitride coating removes the pits, or leaves relatively small protrusions in their place. The protrusions may be removed by a short polishing operation. Other wafer types and etch-resistant materials are possible. Integrated circuits are typically formed on the wafers by lithography techniques that advantageously utilize the improved flatness.

REFERENCES:
patent: 4251300 (1981-02-01), Caldwell
patent: 4278987 (1981-07-01), Imaizumi et al.
patent: 4331546 (1982-01-01), Abe et al.
patent: 4671851 (1987-06-01), Beyer et al.
patent: 4735679 (1988-04-01), Lasky

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