Electrical computers and digital processing systems: virtual mac – Task management or control – Process scheduling
Reexamination Certificate
2006-01-31
2006-01-31
Knight, Anthony (Department: 2121)
Electrical computers and digital processing systems: virtual mac
Task management or control
Process scheduling
C718S103000, C718S105000, C718S104000, C710S244000, C710S264000, C710S266000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06993766
ABSTRACT:
An integrated circuit (7A) for multitasking support for processing unit (1A) holds control variables for each task (or activity) to run on its associated processor (1A) and identifies the next task that should run. The circuit (7A) employs level-driven, clock free ripple logic and is configured as a two dimensional array of “tiles”, each tile being composed of simple logic gates and performing a dedicated function. The circuit has particular application to asynchronous multiple processor networks.
REFERENCES:
patent: 3643227 (1972-02-01), Smith et al.
patent: 4468727 (1984-08-01), Carrison et al.
patent: 4796178 (1989-01-01), Jennings et al.
patent: 4905175 (1990-02-01), Corbett et al.
patent: 4964040 (1990-10-01), Wilcox
patent: 5168566 (1992-12-01), Kuki et al.
patent: 5265203 (1993-11-01), Peaslee et al.
patent: 5469549 (1995-11-01), Simpson et al.
patent: 5487170 (1996-01-01), Bass et al.
patent: 0 155 371 (1985-09-01), None
patent: 0 250 011 (1987-12-01), None
patent: 0 253 970 (1988-01-01), None
patent: 0 266 065 (1988-05-01), None
patent: 0 362 903 (1990-04-01), None
patent: 0 364 000 (1990-04-01), None
patent: 2 244 356 (1991-11-01), None
patent: WO 87/02486 (1987-04-01), None
patent: WO 91 16681 (1991-10-01), None
Perotto et al. “An 8-bit Multitask Micropower RISC Core” Aug. 1994, IEEE Journal of Solid State Circuits, vol. 29 No. 8, pp 986-991.
IBM Technical Disclosure Bulletin, vol. 28, No. 5, Oct. 1985, New York US, pp. 1981-1985, XP002034326 “Procedure for Hierarchical Chip Physical Design” see the whole document.
IEICE Transactions on Electronics, vol. E76-C, No. 11, Nov. 1993, pp. 1641-1648, XP000424603 Nobutar Shibata et al.: “High-Performance Memory Macrocells With Row and Column Sliceable Architecture” see abstract see p. 1652, left-hand column, line 23; figures 1,2.
Campbell Eric R
Simpson Hugo R
Knight Anthony
MBDA UK Limited
Nixon & Vanderhye P.C.
Pham Thomas
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