Integrated circuits and methods to compensate for defective...

Details Integrated circuits and methods to compensate for defective... Integrated circuits and methods to compensate for defective...

2011-03-08

2011-03-08

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S185090, C365S210100

Reexamination Certificate

active

07903485

ABSTRACT:
Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods to compensate for defective memory in third dimension memory technology. In a specific embodiment, an integrated circuit is configured to compensate for defective memory cells. For example, the integrated circuit can include a memory having memory cells that are disposed in multiple layers of memory. It can also include a memory reclamation circuit configured to substitute a subset of the memory cells for one or more defective memory cells. At least one memory cell in the subset of the memory cells resides in a different plane in the memory than at least one of the one or more defective memory cells.

REFERENCES:
patent: 2005/0047226 (2005-03-01), Martinelli et al.
patent: 2005/0057961 (2005-03-01), Ahmad

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