Computer-aided design and analysis of circuits and semiconductor – Design of semiconductor mask or reticle – Layout generation
Reexamination Certificate
2010-07-20
2011-12-13
Garber, Charles (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Design of semiconductor mask or reticle
Layout generation
C716S050000, C716S054000, C716S056000, C716S106000, C716S109000, C716S120000, C716S122000, C716S123000, C716S132000, C716S133000, C257S368000, C257S605000, C257SE27060, C257SE27009
Reexamination Certificate
active
08078998
ABSTRACT:
Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.
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Eller Manfred
Haffner Henning
Lindsay Richard
Abdelaziez Yasser
Garber Charles
Infineon - Technologies AG
Slater & Matsil L.L.P.
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