Integrated circuits and methods of design and manufacture...

Computer-aided design and analysis of circuits and semiconductor – Design of semiconductor mask or reticle – Layout generation

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C716S050000, C716S054000, C716S056000, C716S106000, C716S109000, C716S120000, C716S122000, C716S123000, C716S132000, C716S133000, C257S368000, C257S605000, C257SE27060, C257SE27009

Reexamination Certificate

active

08078998

ABSTRACT:
Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.

REFERENCES:
patent: 5308741 (1994-05-01), Kemp
patent: 5563012 (1996-10-01), Neisser
patent: 5821014 (1998-10-01), Chen et al.
patent: 6421820 (2002-07-01), Mansfield et al.
patent: 6734762 (2004-05-01), Cornett et al.
patent: 6777147 (2004-08-01), Fonseca et al.
patent: 6787469 (2004-09-01), Houston et al.
patent: 6929887 (2005-08-01), Lin et al.
patent: 7495294 (2009-02-01), Higashitani
patent: 2001/0020878 (2001-09-01), Speidell et al.
patent: 2004/0063038 (2004-04-01), Shin et al.
patent: 2004/0068712 (2004-04-01), Heng et al.
patent: 2005/0216873 (2005-09-01), Singh et al.
patent: 2006/0264001 (2006-11-01), Tran et al.
patent: 2008/0014684 (2008-01-01), Blatchford et al.
Haffner, H., et al., “Mastering Double Exposure Process Window Aware OPC by Means of Virtual Targets,” Proc. SPIE Int. Soc. Opt. Eng. 6349, 63491W, 2006, 11 pages.
Meiring, J.E., at al.; “ACLV Driven Double-Patterning Decomposition with Extensively Added Printing Assist Features (PrAFs),” Hopewell Junction, NY; 1983, 12 pages.
Miller, S., et al.; “Lithography Value Drivers in IC Design & Manufacturing,” Semiconductor Fabtech; 30thEdition; pp. 76-83, Jun. 25, 2006.
Rabkin, P., et al.; “Fabless/Foundry DFM: 45nm and Beyond,” Semiconductor Fabtech; 32ndEdition; pp. 76-82, Dec. 1, 2006.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Integrated circuits and methods of design and manufacture... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated circuits and methods of design and manufacture..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuits and methods of design and manufacture... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4309852

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.